Clarence J. Tracy

Characterization of sputtered barium strontium titanate and strontium titanate-thin films

Sputtered Ba1−xSrxTiO3 (BST) and SrTiO3 (STO) films and capacitors made with these dielectrics have been characterized with respect to physical and electrical properties. Specific capacitance values included a high of 96 fF/μm2 for BST films deposited of 600 °C and a high of 26 fF/μm2 for STO films deposited at 400 °C. Leakage current densities at 3.3 V for the most part varied from mid 10−8 to mid 10−6 A/cm2. All of the dielectrics are polycrystalline, although the lowest temperature STO films have a nearly amorphous layer which impacts their capacitance. Grain size increases with deposition temperature, which correlates to higher dielectric constants. The lattice parameter of the BST films is larger than that of bulk samples. Capacitance, leakage, breakdown, and lifetime results are reported.

Model for surface diffusion of aluminum-(1.5%) copper during sputter deposition

Surface diffusion plays a critical role in improving the step coverage of sputter deposited aluminum–copper (Al–Cu) films, which are widely used in the microelectronics industry. Unfortunately, values of surface diffusivity as a function of temperature have not been published for aluminum copper films commonly used. We present a model for surface diffusion during sputter deposition of Al–Cu films and show that semiquantitative agreement with experimental Al–(1.5%)Cu film profiles can be obtained. This modeling and experimental work is a step toward developing a method to estimate diffusivity values using films deposited in process equipment, which would prove useful in process design. Al–(1.5%)Cu films were deposited at 303, 423, 523, and 623 K, into ‘‘infinite’’ trenches which have a variety of initial aspect ratios. No substrate bias was applied in order to minimize resputtering of deposited material. Surface diffusivity as a function of temperature was estimated by comparing experimental film profiles ...

Tightly bound H2O in spin‐on‐glass

The purpose of this work is to measure the amount of H2O which is bound tightly in spin‐on‐glass (SOG) and the amount of reabsorption as a function of room air exposure time. Both results are needed in determining bake cycles and wait times prior to metal deposition when SOG is used in the dielectric stack of a multilevel metal system. About a tenth of the amount of gas which remains after a 2 h 150 °C bake is still present after a 2 h 350 °C bake. About half the amount of the tightly bound gas which is desorbed will be reabsorbed upon exposure to air in a period of 4 h or less. The time for half of the reabsorption to occur appears to be of the order of 20 to 60 min.

An inorganic anti-reflective coating for use in photolithography

In this work, we discuss the design of an inorganic anti‐reflective coating for use in photolithography at a wavelength of 3650 A (I line). We consider the effect of the optical constants on the reflectance and show that when the extinction coefficient, k, of the film has a value near 0.8, the reflectance will be very small for a range of values of the thickness and the index of refraction, n. We illustrate the principle with one example where we use a combination of TiW and the oxide of TiW. Reflectance is measured for a range of thicknesses of both the TiW and the oxide of TiW. Values less than 5% were obtained.

A high performance, four metal layer interconnect system for bipolar and BiCMOS circuits

Two similar four-layer metal systems have been developed to meet the requirements of MOSAIC IV and V high-performance bipolar and BiCMOS circuits. These systems have planarized surfaces obtained using an n-layer photoresist and etchback processes with PETEOS as an interlayer dielectric (ILD). The high-aspect-ratio vias are filled with a multistep hot sputtered Al process. CVD W is also being evaluated as a via fill process. The initial design rules were based on the circuit goals, performance modeling, process and material capabilities, and reliability goals. The development of these processes and the design rule selection process are discussed. Test vehicles were built, and the processes and modeling were verified. Results from the test vehicles as well as a MOSAIC IV demonstration circuit are presented.<<ETX>>

Barium Strontium Titanate Capacitors for Embedded Dram

Long recognized as the best potential solution to the continued scaling of the onetransistor/one-capacitor standalone dynamic random access memory (DRAM) beyond a gigabit, barium strontium titanate (BST) and other high permittivity dielectrics are fast becoming enablers to embedding large amounts of memory into a high performance logic process. System requirements such as granularity, bandwidth, fill frequency, and power pose major challenges to the use of high density standalone DRAM, leading to the current push for embedded solutions where very wide buses are possible. As a result, projected embedded memory sizes are rapidly approaching that of the standalone products, and with the high wafer cost of the combined logic plus memory process, bit cell scaling is critical. The BST memory cell, with its low thermal budget processing, very high charge storage density, and high conductivity metal electrodes has the potential to be efficiently embedded with traditional logic flows if the materials and integration challenges of the required three dimensional (3D) bit cell capacitors can be solved. BST materials properties such as dielectric relaxation, interface capacitance, and resistance degradation and their impact on capacitor scaling will be reviewed along with the electrode materials issues associated with certain 3D capacitor designs. The scaling limits of BST bit cells in the deep sub-micron regime will be discussed.

Stoichiometric Effects of Sputtered Barium Strontium Titanate Films

Barium Strontium Titanate films have been deposited by rf magnetron sputtering and have been studied with respect to Ba/Sr ratio. Physical and electrical characterization has been done as a function of temperature, thickness, and composition, and results show that dielectric constant increases with increasing temperature, thickness (up to ∼80 nm), and Ba/Sr ratio for the compositions studied. The lattice parameters for the sputtered films are larger than those expected for powder samples and also increase with increasing Ba/Sr ratio.

Control of stress-void formation in aluminum-copper filled vias

A four layer metal system, designed for high speed bipolar gate arrays, subjected to high temperature aging was found to contain mechanical stress induced voids at the metal to metal interfaces within micron and sub-micron vias. The interconnect metal used in the system, AlCu(1.5%) sputter deposited at high temperatures, literally fills the vias and is quite resistant to stress voiding in the lines. However, thermal aging at 200 degree(s)C with no current flow led to open circuit failures of the 0.8 micron stacked via structures where via two is place directly over via one, and within via one and via two chains as well. The time to failure was studied as a function of temperature, via dimension, and processing changes to both the surrounding dielectric and the metallization. Reliability studies of the original, unmodified via structure, as well as those with process changes as indicated above have identified some of the significant factors affecting stress controlled via reliability.

Plasma Processing in Semiconductor Manufacturing

The implementation of plasma deposition and reactive ion etching into a semiconductor VLSI manufacturing process is rarely trivial.In some cases isolated process modules may appear to function well until integrated into a lengthy product flow, where interactions occur with prior or subsequent processing steps.In addition, dry processes have some unique and sometimes undesirable characteristics which need to be considered.Examples of both of these kinds of problems will be shown.Opportunities still exist for research to lead to a better understanding of mechanisms and for development work to improve the equipment and specific processes.