Peter Fejes

Two-dimensional growth of high-quality strontium titanate thin films on Si

Most semiconductor materials such as Si, Ge, and GaAs are subject to oxidation when exposed to oxidants. This results in difficulties in the heterointegration of epitaxial oxides on these semiconductors. Even though certain oxides may be thermodynamically stable when placed in contact with semiconductors, direct epitaxy of these oxides encounters kinetic difficulties due to the loss of epitaxy caused by the formation of an amorphous oxide at the interface. In this article, we address some important issues on the heteroepitaxy of oxides on semiconductors and show a stepped growth method that utilizes the kinetic characteristics of the growth process to suppress the oxidation of the substrate surface and thereby achieve oxide films with a high degree of crystallinity. The epitaxy of high-quality SrTiO3 (STO) thin films directly on Si was achieved. The chemical and structural properties of the STO/Si interface were evaluated in situ using reflection high-energy electron diffraction, x-ray photoelectron spect...

Characterization of sputtered barium strontium titanate and strontium titanate-thin films

Sputtered Ba1−xSrxTiO3 (BST) and SrTiO3 (STO) films and capacitors made with these dielectrics have been characterized with respect to physical and electrical properties. Specific capacitance values included a high of 96 fF/μm2 for BST films deposited of 600 °C and a high of 26 fF/μm2 for STO films deposited at 400 °C. Leakage current densities at 3.3 V for the most part varied from mid 10−8 to mid 10−6 A/cm2. All of the dielectrics are polycrystalline, although the lowest temperature STO films have a nearly amorphous layer which impacts their capacitance. Grain size increases with deposition temperature, which correlates to higher dielectric constants. The lattice parameter of the BST films is larger than that of bulk samples. Capacitance, leakage, breakdown, and lifetime results are reported.

Optical properties of bulk and thin-film SrTiO3 on Si and Pt

We have studied the optical properties (complex dielectric function) of bulk SrTiO3 and thin films on Si and Pt using spectroscopic ellipsometry over a very broad spectral range, starting at 0.03 eV [using Fourier transform infrared (FTIR) ellipsometry] to 8.7 eV. In the bulk crystals, we analyze the interband transitions in the spectra to determine the critical-point parameters. To interpret these transitions, we performed band structure calculations based on ab initio pseudopotentials within the local-density approximation. The dielectric function was also calculated within this framework and compared with our ellipsometry data. In the FTIR ellipsometry data, we notice a strong lattice absorption peak due to oxygen-related vibrations. Two longitudinal optic (LO) phonons were also identified. In SrTiO3 films on Si, the refractive index below the band gap decreases with decreasing thickness because of the increasing influence of the amorphous interfacial layer between the SrTiO3 film and the Si substrate....

Characteristics of spin-on ferroelectric SrBi 2 Ta 2 O 9 thin film capacitors for ferroelectric random access memory applications

We report on the properties and characterization of SrBi 2 Ta 2 O 9 (SBT, or Y − 1) thin film capacitors for ferroelectric random access memory (FERAM) applications. The films were prepared by spin-coating from carboxylate precursors. The remanent polarization ( P r ) was 5−6 μ C/cm 2 and the coercive field was ∼55 kV/cm. Excellent fatigue endurance was observed up to 10 11 cycles. Auger analysis indicates bismuth diffusion through the Pt electrode after capacitor anneal which might require excess Bi in the precursor solution for stoichiometry control. No detectable amount of α emission was found from SBT films, which reduces the possibility of soft error when used in the memory devices.

1-

In this letter, 1-mum GaAs-based enhancement-mode n-channel devices with channel mobility of 5500 cm²/Vmiddots and g _m exceeding 250 mS/mm have been fabricated. The measured device parameters including threshold voltage V_th, maximum extrinsic transconductance g_m, saturation current I_dss, on-resistance R_on, and gate current are 0.11 V, 254 mS/mm, 380 mA/mm, 4.5 Omegamiddotmm, and < 56 pA for a first wafer and 0.08 V, 229 mS/mm, 443 mA/mm, 4.5 Omegamiddotmm, and < 90 pA for a second wafer, respectively. With an intrinsic transconductance g_mi of 434 mS/mm, GaAs enhancement-mode MOSFETs have reached expected intrinsic device performance

\mu\hbox{m}

Hypoeutectic AuGe/Ni ohmic contacts on GaAs and GaAs/AlGaAs were characterized by SEM, TEM, and energy dispersive X-ray analysis. The two main components of the contact were confirmed to be NiGeAs islands distributed in an Au-Ga alloy. The NiGeAs islands were larger and more evenly distributed on GaAs MESFETs than on GaAs/AlGaAs MODFETs. Vertical penetration was impeded but not halted by AlGaAs. Since the contacts did not melt during the alloying cycle, there was no lateral encroachment observed. >

Enhancement Mode GaAs N-Channel MOSFETs With Transconductance Exceeding 250 mS/mm

Electrical properties of Ga₂O₃/GaAs interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm (0.9 les EOT les 3.9 nm) have been characterized by capacitance-voltage measurements. Midgap interface state density D_it, effective workfunction phi_m, fixed charge Q_f, dielectric constant kappa, and low field leakage current density are 2 times10¹¹ cm^-2 middoteV^-1, 4.93 eV, -8.9 times10¹¹ cm^-2, 19.5, and 10^-9- 10^-8 A/cm², respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.

Ohmic contact penetration and encroachment in GaAs/AlGaAs and GaAs FETs

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V/sub TP/) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V/sub TP/ shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO/sub 2//Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V/sub TP/ shift. >

Electrical Properties of

Step and Flash Imprint Lithography (SFIL) is a revolutionary next generation lithography option that has become increasingly attractive in recent years. Elimination of the costly optics of current step and scan imaging tools makes SFIL a serious candidate for large-scale commercial patterning of critical dimensions below ~50 nm. This work focuses on the kinetics of the UV curing of the liquid etch barrier and the resulting densification/contraction of the etch barrier as it solidifies during this step. Previous experimental work in our group has measured the bulk densification of several etch barrier formulations, typically about 9 % (v/v). It remains unknown, however, how much etch barrier contraction occurs during the formation of nano-scale features. Furthermore, it is of interest to examine how changes in monomer pendant group size impact imprinted feature profiles. This work provides answers to these questions through a combination of modeling and experimental efforts. Densification due to the photopolymerization reaction and the resulting shift from Van der Waals’ to covalent interactions is modeled using Monte-Carlo techniques. The model allows for determination of extent of reaction, degree of polymerization, and local density changes as a function of the etch barrier formulation and the interaction energies between molecules (including the quartz template). Experimental efforts focus on a new technique to examine trench profiles in the quartz template using TEM characterization. Additionally, SEM images of imprinted images from various etch barrier formulations were examined to determine local contraction of the etch barrier. Over a large range of etch barrier formulations, which range from 10 - 20 % volumetric contraction as bulk materials, it was found that dense 100 nm lines printed approximately the same size and shape.

\hbox{Ga}_{2}\hbox{O}_{3}/ \hbox{GaAs}

The effect of poly-gate sidewall oxidation on short-channel MOSFET behavior is examined. The gain, threshold voltage, and apparent electrical channel length are shown to be very sensitive to the location of the n/sup -/ junction edge with respect to the poly-gate edge for a lightly-doped-drain NMOS transistor. New guidelines for the design of submicrometer MOSFETs based on an analysis of the sidewall oxidation of the polysilicon after gate definition are proposed.<<ETX>>