Clarence W. Teng

Interface trap-enhanced gate-induced leakage current in MOSFET

Interface traps are shown to significantly affect the gate-induced drain-leakage current in a MOSFET or gated diode. The leakage current in a p/sup +/-gated diode can increase by two orders of magnitude when the interface trap density is increased from 10/sup 11/ to 10/sup 12/ cm/sup -2/-eV/sup -1/. The fact that thermal annealing at 300 degrees C can eliminate both the generated interface traps and the excessive leakage current supports the close correlation between the two. The p/sup +/-gated diode is found to be more susceptible to this interface-trap related leakage current than the n/sup +/-device, which can be explained qualitatively by an interface-trap-assisted tunneling model.<<ETX>>

Soft breakdown in titanium-silicided shallow source/drain junctions

Electrical characterization of the leakage current in p/sup +//n shallow junctions (X/sub j/=130 nm) shows that the current increases dramatically with titanium thickness and strongly depends on the reverse-bias voltage. The activation energy of leakage current extracted from the temperature dependence of the current decreases with increasing reverse-bias voltage. This behavior cannot be explained by the Shockley-Hall-Read (SHR) generation-recombination mechanism. A mechanism involving Frenkel-Poole barrier lowering of a trap potential is proposed.<<ETX>>

A quantitative physical model for the band-to-band tunneling-induced substrate hot electron injection in MOS devices

A quantitative physical model for band-to-band tunneling-induced substrate hot electron (BBISHE) injection in heavily doped n-channel MOSFETs is presented. In BBISHE injection, the injected substrate hot electrons across the gate oxide are generated by impact ionization by the energetic holes which are left behind by the tunneling electrons and become energetic when traveling across the surface high-field region in silicon. The finite available distance for the holes to gain energy for impact ionization is taken into account. A previously published theory of substrate hot electron injection is generalized to account for the spatially distributed nature of the injected electrons. This model is shown to be able to reproduce the I-V characteristics of the BBISHE injection for devices with different oxide thicknesses and substrate dopant concentration biased in inversion or deep depletion. Moreover, it is shown that the effective SiO/sub 2/ barrier height for over-the-barrier substrate hot electron injection is more accurately modeled. >

Gate current injection initiated by electron band-to-band tunneling in MOS devices

A substrate hot-electron injection across the gate oxide initiated by electron band-to-band tunneling in p-type silicon is discussed. The injection electrons are generated by the energetic holes which are originally left behind by the band-to-band tunneling electrons. The injection can be easily controlled by an appropriate bias to a nearby n/sup +/ diffusion, and the injection efficiency can be as high as 10/sup -2/. Due to the small oxide field during injection, the electron fluence through the oxide before failure is much higher than under a Fowler-Nordheim tunneling stressing. These advantages make this band-to-band tunneling induced substrate hot-electron injection a possible programming mechanism for nonvolatile memories.<<ETX>>

Defect generation in trench isolation

Defect generation in silicon during trench isolation process has been studied. Several sources of defect generation have been identified using Secco etching. These include contamination from the redeposited oxide layer during the trench etch and the stress induced at trench corners during the trench cap and field oxidation. A Sealed Sidewall Trench (SST) isolation process has been developed which results in defect-free trench isolation structures. A key addition to the refill dielectrics in SST is the incorporation of nitride layer(s) for inhibiting excessive vertical birds beaking.

Anomalous current‐voltage behavior in titanium‐silicided shallow source/drain junctions

The anomalous behavior of forward and reverse bias current versus applied voltage in titanium‐silicided shallow source/drain junctions has been studied. The reverse leakage current characteristics in p+/n shallow junctions (Xj=130 nm) show that the current increases rapidly with titanium thickness and exponentially depends on the reverse bias voltage, while the activation energy of leakage current extracted from the temperature dependence of the current decreases with increasing reverse bias voltage. Forward current in a silicided junction is characterized at low temperatures for the first time. The ideality factor of the forward current increases as temperature decreases and has values higher than 2 at very low temperatures. This behavior cannot be explained by the field‐independent Shockley‐Hall‐Read generation‐recombination mechanism. A new mechanism involving the Frenkel–Poole barrier lowering of a trap potential is proposed.

Simple gate-to-drain overlapped MOSFETs using poly spacers for high immunity to channel hot-electron degradation

Short n-channel MOSFETs with permanent poly spacers over the lightly doped drain (LDD) region are demonstrated to be effective in increasing the resistance to channel hot-electron-induced degradation. The hot-electron lifetime of the poly-spacer devices is two to three orders of magnitude longer than that of a conventional oxide-spacer device. This improvement is entirely due to the reduced electron trapping in the gate oxide under the sidewall spacer. The disadvantages of the poly-spacer devices, higher gate-to-drain overlap capacitance and weaker gate oxide integrity, can both be minimized to within 20% of those of the oxide-spacer device by a short oxidation before the formation of the poly spacer.<<ETX>>

Scalability of a trench capacitor cell for 64 Mbit DRAM

The authors address cell leakage issues and conclude that a unique field-plate isolated trench capacitor cell structure, already demonstrated at the 16-Mb level with over 1 s of data retention (50% bit fail measured at 90 degrees C), is scalable to 64-Mb DRAM (dynamic RAM). As the trench size is reduced to 0.6 mu m, the trench curvature helps reduce the trench-to-trench punch-through leakage. Substrate concentration of approximately 10/sup 17/ cm/sup -3/ is sufficient to suppress the punch-through current with a 0.5- mu m trench spacing. Diode and gate-induced breakdown voltages remain well above the operating voltage. Trench capacitor dielectric is scalable to less than 5-nm equivalent oxide thickness.<<ETX>>

A sub-half micron partially gate-to-drain overlapped MOSFET optimized for high performance and reliability

A partially gate-to-drain overlapped n-channel MOSFET using poly spacers was studied and compared to a fully overlapped and a conventional oxide spacer device in terms of performance and reliability. It is shown that, for a 500-AA partial overlap (flanked with 700-AA oxide spacer) device, the gate-to-drain overlap capacitance and simulated inverter delay are only 12% and 8%, respectively, higher than those of a conventional oxide spacer device. At a given performance level, the partial overlap device has two orders of magnitude longer DC hot-carrier lifetime than that of an oxide spacer device. The reason the overlapped device has high resistance to the hot-carrier stressing is the adverse oxide field at V/sub G/<V/sub D/ for the hot electrons to create damage under the spacer. The minimum gate-to-drain overlap distance maintaining the high reliability is roughly estimated to be around 200 to 300 AA for the current devices. The feasibility of selective removal of the poly spacers on p-channel and some layout-critical n-channel devices is demonstrated.<<ETX>>

DRAM technology trend

During the last few years new DRAM products have been introduced at a rate of -4 years/generation instead of 3. This trend will continue. Chip design efficiency (defined as the ratio between cell and total chip area) must be increased to >60-65% for 1 Gb and beyond. Self-alignment schemes are essential for 64 Mbit and beyond but after the first generation of 1 Gb additional technology breakthroughs are needed for a cell area of less than 8F/sup 2/ where F is design size. Conventional nitride storage dielectric, in conjunction with capacitor area enhancement techniques like HSG (hemispheric grain) and corrugated cylindrical poly electrodes, is applicable for 256 Mbit and possibly first generation 1 Gb. Barium strontium titanate will be used for 1 Gb products and beyond.