Robert R. Doering

Conduction mechanisms in sputtered Ta2O5 on Si with an interfacial SiO2 layer

The temperature dependence of leakage in sputtered Ta2O5 films (10–30 nm) on Si substrates with an interfacial SiO2 layer has been studied for temperatures between –50 and +100 °C and for electric fields between 0 and 2 MV/cm. The activation energy of leakage and the current‐voltage relationships have been used to identify various high field conduction mechanisms such as Poole–Frenkel transport at high temperatures and field emission at low temperatures. At low fields and intermediate temperatures, electronic hopping conduction leading to space‐charge‐limited flow at high current densities has been observed.

Conduction mechanisms in sputtered Ta/sub 2/O/sub 5/ on Si with an interfacial SiO/sub 2/ layer

The temperature dependence of leakage in sputtered Ta2O5 films (10–30 nm) on Si substrates with an interfacial SiO2 layer has been studied for temperatures between –50 and +100 °C and for electric fields between 0 and 2 MV/cm. The activation energy of leakage and the current‐voltage relationships have been used to identify various high field conduction mechanisms such as Poole–Frenkel transport at high temperatures and field emission at low temperatures. At low fields and intermediate temperatures, electronic hopping conduction leading to space‐charge‐limited flow at high current densities has been observed.

Limits of integrated-circuit manufacturing

A methodology is suggested for the study of integrated-circuit manufacturing limits. It is based on a hierarchical view of manufacturing detractors and associates limits with levels in this hierarchy. The methodology is illustrated with examples of steady-state, theoretical, and process limits at todays state of the art as well as example projections to future manufacturing at what may be near the limits of complementary metal-oxide-semiconductor (CMOS) scaling. There are also some speculations on possibilities beyond these limits.

Trends in single-wafer processing

It is pointed out that one of the most significant trends in semiconductor manufacturing over the past three decades has been the gradual replacement of batch processing with single-wafer processing. Two other trends, the use of larger silicon wafers (to reduce manufacturing cost) and the necessity for more demanding process-performance specifications (to allow continued device circuit scaling), have driven this move to single-wafer equipment for many processes. It is now technically feasible to produce silicon integrated circuits with 100% single-wafer processing. In the next decade, it may also become economically feasible to do so.<<ETX>>

Manufacturability Issues Of The DESIRE Process

Surface-imaging schemes are an attractive alternative to overcome many of the limitations optical microlithography is presently facing. A good example of this type of approach is the so-called DESIRE process. A preliminary performance characterization of the DESIRE process showed a significant increase in resolution and process latitude. However, new process variables must be understood and technical challenges overcome before this process can be successfully implemented in a manufacturing environment. The purpose of this paper is to explore these new process variables and suggest solutions for the implementation of the DESIRE process in high-volume production of semiconductor devices.

A high quality high temperature compatible Tantalum oxide film for advanced dRAM applications

A reactive sputtering technique was used for the preparation of Ta<inf>2</inf>O<inf>5</inf>films on Si substrates. The film was found either comparable or superior to the best results reported in the literature [1-5] in breakdown field strength, dielectric constant and/or leakage current. Thermal oxidation of the Ta<inf>2</inf>O<inf>5</inf>film resulted in the growth of SiO<inf>2</inf>under Ta<inf>2</inf>O<inf>5</inf>. The electrical characteristics of the oxidized film were close to pure SiO<inf>2</inf>with an advantage of 20% higher storage charge density. From underlying silicon oxidation kinetics, an activation energy of 0.9 eV was found for the oxygen diffusion in Ta<inf>2</inf>O<inf>5</inf>. The Ta<inf>2</inf>O<inf>5</inf>film has shown potential for applications in advanced dRAMs.

Properties of trench capacitors for high density DRAM applications

Due to increasing levels of integration, it is expected that next generation DRAMs will make use of trench capacitors to minimize the area of a cell. In this paper we examine the properties of oxides grown in trenches and compare them with comparable oxides grown on planar surfaces. We also examine the effects of various cell to cell spacing on the trench to trench leakage. We conclude that despite the challenges of trench technology, it is excellent for use in 1Mbit and 4Mbit DRAMS.

Manufacturing gigachips in the year 2005

10 years from now, we envision producing gigachips for an ever expanding electronics market at a cost per function that continues to decrease by approximately 25%/year. To meet this challenge, we must continue to pursue advanced concepts in factories and equipment that are synergistic with continuous/synchronous manufacturing. In particular, such opportunities include: larger wafers, single-wafer processing, clustering/multiprocessing, real-time process/factory control, integrated minienvironments, and standards-based modular design. In most cases, the development and implementation of such change will require new levels of cooperation among suppliers, customers, and competitors in the semiconductor industry.

Real-time measurement for fast cycle time

Summary form only given. The most challenging overall goal of the Microelectronics Manufacturing Science and Technology (MMST) Program was the demonstration of 3-day cycle time for manufacturing double-level-metal 0.35-/spl mu/m CMOS circuits. Achievement of this goal was enabled by development of: (1) a 100% single-wafer processing facility and (2) a substantial implementation of real-time process and factory control. In this paper, we focus on the relationship between cycle time and real-time control.

Submicron Single-Layer Lithography Using Reactive Ion Etching

This paper describes the application of reactive ion etching to submicron single-layer lithography. It is shown that the etch selectivity of silicon containing resists is a strong function of the ion energy; that is, the selectivity increases for low ion energies. That supports the use of magnetically enhanced ion etchers for the development of single-layer silylated photoresists since the ion energy in these reactors is low for most process conditions. This paper shows that by a proper design of the reactor and the process good selectivity can also be achieved in a reactive ion etcher. This allows for the use of a simple reactor for some dry-develop lithography applications. The conditions leading to good selectivity as well as several submicron applications are described in this paper.