Ih-Chin Chen

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

This paper reports a full CMOS process using a combination of a TiN/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gate capacitances equivalent to that for <2 nm SiO/sub 2/ but having relatively low gate leakage are reported. Transistors with gate lengths near or below 0.1 /spl mu/m have good characteristics. Working CMOS circuits using Ta/sub 2/O/sub 5/ gate insulator are demonstrated for the first time.

Conduction mechanisms in sputtered Ta2O5 on Si with an interfacial SiO2 layer

The temperature dependence of leakage in sputtered Ta2O5 films (10–30 nm) on Si substrates with an interfacial SiO2 layer has been studied for temperatures between –50 and +100 °C and for electric fields between 0 and 2 MV/cm. The activation energy of leakage and the current‐voltage relationships have been used to identify various high field conduction mechanisms such as Poole–Frenkel transport at high temperatures and field emission at low temperatures. At low fields and intermediate temperatures, electronic hopping conduction leading to space‐charge‐limited flow at high current densities has been observed.

Interface trap-enhanced gate-induced leakage current in MOSFET

Interface traps are shown to significantly affect the gate-induced drain-leakage current in a MOSFET or gated diode. The leakage current in a p/sup +/-gated diode can increase by two orders of magnitude when the interface trap density is increased from 10/sup 11/ to 10/sup 12/ cm/sup -2/-eV/sup -1/. The fact that thermal annealing at 300 degrees C can eliminate both the generated interface traps and the excessive leakage current supports the close correlation between the two. The p/sup +/-gated diode is found to be more susceptible to this interface-trap related leakage current than the n/sup +/-device, which can be explained qualitatively by an interface-trap-assisted tunneling model.<<ETX>>

Shallow trench isolation for advanced ULSI CMOS technologies

This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 /spl mu/m CMOS technologies. Various processing techniques are described for the steps in the STI flow viz. trench definition, corner rounding, gapfill, planarization and well implants. The current capability and scaling requirements for each process step, discussed in the paper, are as follows: (a) Trenches have sidewall angle >/spl sim/80/spl deg/ to maintain trench depth and isolation at narrow space. The trench bottom is rounded to minimize stress. (b) Pad oxide undercut, prior to liner oxidation in halogen ambient or at high temperature, provides adequate corner rounding to suppress edge leakage, with minimum loss of active area. (c) HDP and TEOS-O/sub 3/ CVD oxides can fill 0.16 /spl mu/m wide trenches free of voids. Lower trench aspect ratios (thinner nitride and liner oxide, and shallower trenches), and process improvements allow scaling to smaller dimensions. Gapfill process, liner oxide, and thermal cycles are tailored to prevent stress-induced defects, trench sidewall and corner damage. (d) CMP step height uniformity is improved by using dummy active areas, nitride overlayer or patterned etchback. (e) Optimization of retrograde well and channel stop implants minimizes sensitivity of N/sup +/-P/sup +/ isolation to overlay tolerance and improves latch-up performance.

Conduction mechanisms in sputtered Ta/sub 2/O/sub 5/ on Si with an interfacial SiO/sub 2/ layer

The temperature dependence of leakage in sputtered Ta2O5 films (10–30 nm) on Si substrates with an interfacial SiO2 layer has been studied for temperatures between –50 and +100 °C and for electric fields between 0 and 2 MV/cm. The activation energy of leakage and the current‐voltage relationships have been used to identify various high field conduction mechanisms such as Poole–Frenkel transport at high temperatures and field emission at low temperatures. At low fields and intermediate temperatures, electronic hopping conduction leading to space‐charge‐limited flow at high current densities has been observed.

Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process

A novel replacement gate design with 1.5-3 nm oxide or remote plasma nitrided oxide gate insulators for sub-100 nm Al/TiN or W/TiN metal gate nMOSFETs is demonstrated. The source/drain regions are self-aligned to a poly gate which is later replaced by the metal gate. This allows the temperatures after metal gate definition to be limited to 450/spl deg/C. Compared to pure SiO/sub 2/, the nitrided oxides provide increased capacitance with less penalty in increased gate current. A saturation transconductance (g/sub m/) of 1000 mS/mm is obtained for L/sub gate/=70 nm and t/sub OX/=1.5 nm. Peak cutoff frequency (f/sub T/) of 120 GHz and a low minimum noise figure (NF/sub min/) of 0.5 dB with associated gain of 19 dB are obtained for t/sub OX/=2 nm and L/sub gate/=80 nm.

Physical oxide thickness extraction and verification using quantum mechanical simulation

Physical gate oxide thickness is extracted from TiN gate PMOS and NMOS capacitance voltage measurements using an efficient multi-band Hartree self-consistent Poisson solver. The extracted oxide thicknesses are then used to perform direct tunneling current simulations. Excellent agreement between measured a simulated tunnel current is obtained without the use of adjustable fitting parameters.

Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyond

We demonstrate the feasibility of using W/TiN as metal-gate on thin gate dielectrics (/spl les/33 /spl Aring/) and with high temperature (>950/spl deg/C) S/D annealing for 0.13 /spl mu/m CMOS applications. Close to ideal C-V characteristics are obtained indicating good Si/SiO/sub 2/ interface quality and free from gate depletion. The gate sheet resistance is about 2 ohm//spl square/, nearly constant down to 0.05 /spl mu/m. Under fixed effective fields, the electron and hole mobility are comparable to or slightly better than those of poly gate devices. Compared to poly gate devices, the W/TiN on 33 /spl Aring/ pure oxide has inferior charge-to-breakdown (Q/sub bd/) distribution under substrate (+V/sub G/) injection. However, a remote-plasma nitrided oxide (RPNO) can greatly improve the +V/sub G/ Q/sub bd/ distribution for the W/TiN case. Short-channel W/TiN pMOS transistors are fabricated with excellent characteristics down to L/sub gate//spl ap/0.07 /spl mu/m. For nMOS under +V/sub G/ direct tunneling (DT) or Fowler-Nordheim (F-N) tunneling injection with S/D grounded, the W/TiN device has a higher substrate hole current density (J/sub p/) than n/sup +/ poly-gate device (by about an order magnitude larger). This higher J/sub p/ is believed due to the tunneling of valence-band electron and thus has no impact on the thin (t/sub ox//spl les/33 /spl Aring/) gate oxide reliability.

A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 /spl mu/m CMOS technologies and beyond

Shallow trench isolation schemes using a LOCOS edge to avoid sharp corner effects are applied to 0.25 /spl mu/m and 0.18 /spl mu/m technologies. Two variations are studied. In the first case (Case A) a mini-LOCOS is grown and deglazed prior to trench etch whereas in the second case (Case B) the deglaze is omitted. Excellent narrow width effect is demonstrated. The V/sub T/ increases by /spl les/50 mV when the transistor width is reduced from 10 /spl mu/m to 0.3 /spl mu/m. Minimum isolation space of 0.3 /spl mu/m and minimum n/sup +/-to-p/sup +/ space of 0.6 /spl mu/m across a well boundary are demonstrated. Diode leakages and oxide reliability are reasonable. Transistor subthreshold characteristics show no double hump for Case A, while for Case B some devices indicate presence of double hump when a substrate back bias is applied. Despite the mini-LOCOS formation the width reductions are /spl les/0.05 /spl mu/m and excellent drive currents of 660 /spl mu/A//spl mu/m (NMOS) and 290 /spl mu/A//spl mu/m (PMOS) are achieved corresponding to I/sub off/=1 nA//spl mu/m and V/sub cc/=1.8 V.

Comparative evaluation of gap-fill dielectrics in shallow trench isolation for sub-0.25 /spl mu/m technologies

The dielectric material used to fill trenches in Shallow Trench Isolation (STI) of transistors, is key to device performance. This paper (a) evaluates the integration of currently available dielectric technologies and (b) designs an optimized process scheme for 0.25 /spl mu/m node and beyond. A detailed study of LPCVD TEOS, SACVD oxide, Hydrogen-Silsesquioxane SOG (HSQ) and ICP (Inductively Coupled) HDP (High Density Plasma) CVD oxide, for STI, is presented for the first time. A novel ICP HDP-CVD process scheme is shown to have the advantages of single step, low thermal budget and high throughput as well as provide good gap-fill, low HF etch rate, low moisture uptake, low shrinkage with annealing, low diode reverse leakage and isolation at 0.3 /spl mu/m spacing.