Clay S. Gloster

Boundary scan with cellular-based built-in self-test

Boundary scan merging with built-in self-test is discussed. The proposed implementation of boundary scan represents a snapshot of the Joint Test Advisory Group Recommendation 1.0, while the built-in self-test implements the features of cellular automata. Test patterns generated from two distinct sources are examined, one with registers using cellular automata and the other, based on the conventional LFSR (linear-feedback shift register) configuration. Distinctive effects of these patterns on fault coverage of specific designs are analyzed and illustrated.<<ETX>>

Parallel image processing with the block data parallel architecture

Many digital signal and image processing algorithms can be speeded up by executing them in parallel on multiple processors. The speed of parallel execution is limited by the need for communication and synchronization between processors. In this paper, we present a paradigm for parallel processing that we call the block data flow paradigm (BDFP). The goal of this paradigm is to reduce interprocessor communication and relax the synchronization requirements for such applications. We present the block data parallel architecture which implements this paradigm, and we present methods for mapping algorithms onto this architecture. We illustrate this methodology for several applications including two-dimensional (2-D) digital filters, the 2-D discrete cosine transform, QR decomposition of a matrix and Cholesky factorization of a matrix. We analyze the resulting system performance for these applications with regard to speedup and efficiency as the number of processors increases. Our results demonstrate that the block data parallel architecture is a flexible, high-performance solution for numerous digital signal and image processing algorithms.

An acceleration framework for synthetic aperture radar algorithms

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration. We used SAR as a case study to illustrate the potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show a linear speedup by adding reasonably small processing elements in Field Programmable Gate Array (FPGA) as opposed to using a software implementation running on a typical general purpose processor.

Partial scan selection for user-specified fault coverage

With current approaches to partial scan, it is difficult, and often impossible, to achieve a specific level of fault coverage without returning to fill scan. In this paper, we introduce a new formulation of the minimum scan chain assignment problem and propose an effective covering algorithm and test sequence generator SCORCH (Scan Chain Ordering with Reduced Cover Heuristic) to solve it. SCORCH uses a combinational test generator not only to optimize the scan chain assignment, subject to maintaining a user-specified level of fault coverage, brit also as a basis for the test sequence generation. We report experimental results with minimized partial scan assignment and 100% fault coverage for a set of large benchmarks.

Synthesis of weighted random sequences with application to testing of sequential circuits

The weights are stored and a weighted random sequence generator is used to produce the required test sequences during testing rather than storing the actual test sequence themselves. The generation of required weights is based on the dynamic scan algorithm, DYNASTEE. Experimental results demonstrate tradeoffs in test application time and in tester memory requirements, while maintaining 100% fault coverage of all target faults.<<ETX>>

Cellular Scan Revisited

In this paper, we re-examine the concept of test machine embedding and present a specific test machine architecture: cellular scan. This architecture offers advantages both over traditional scan as well as circular scan. Compared to traditional scan, cellular scan shortens required test time with vectors generated deterministically. Compared to circular scan, cellular scan requires less hardware, has no limitations on state coverage, and can significantly improve random pattern testability of sequential logic.