Winser E. Alexander

Multiprocessor implementation of 2-D denominator-separable digital filters for real-time processing

The problem of realizing 2-D denominator-separable digital filters is considered. Four realizations are derived with emphasis on real-time processing in a multiprocessor environment. This implies maximizing parallelism and pipelining, minimizing data throughput delay, and developing computational primitives which can be used as building blocks for very-large-scale integrated-circuit (VLSI) implementation. Advantage is taken of well-known realization structures for 1-D systems in developing the derivations. The performance of each realization is evaluated using criteria appropriate for real-time processing and multiprocessor implementation. It is shown that a simple computational primitive of one multiplier and one adder can be used to realize the filter with data throughput delay time equal to the time required for one multiplication and one addition, independent of the order of the filter. However, the number of required processors is different for each realization, and thus each realization has a different efficiency measure. >

Fault diagnosis in analog circuits using element modulation

Analog fault diagnostic methods are reviewed. A branch fault-diagnosis technique that requires a single excitation source at one test frequency is introduced. The technique lets users construct linearly independent branch-diagnosis equations by modulating selected network elements. An example of the technique applied to a two-stage amplifier is given.<<ETX>>

A mean field annealing approach to robust corner detection

This paper is an extension of our previous paper to improve the capability of detecting corners. We proposed a method of boundary smoothing for curvature estimation using a constrained regularization technique in the previous paper. We propose another approach to boundary smoothing for curvature estimation in this paper to improve the capability of detecting corners. The method is based on a minimization strategy known as mean field annealing which is a deterministic approximation to simulated annealing. It removes the noise while preserving corners very well. Thus, we can detect corners easier and better in this approach than in the constrained regularization approach. Finally, some matching results based on the corners detected by corner sharpness in the mean field annealing approach are presented as a demonstration of the power of the proposed algorithm.

A novel VLSI architecture for the real-time implementation of 2-D signal processing systems

The authors present a high-performance VLSI architecture for two-dimensional (2-D) digital signal processing applications. The architecture uses a specially designed digital signal processor (DSP) as a node in a multiprocessor system for real-time or near-real-time 2-D signal processing. The DSP is custom-designed and has a throughput of two multiplications and three additions in a single cycle. It has wavefront-array-processor properties and operates asynchronously in a multiprocessor system. This architecture extends the concept of using a single processor to the use of a multiprocessor system.<<ETX>>

An optimum solution for scale-invariant object recognition based on the multiresolution approximation

This paper presents a multiresolution approximation approach to obtaining boundary representations for object recognition. Our technique combines a multiresolution approximation and the curvature scale-space representation for obtaining representations. Our research consists of two main parts. In the first part of our research, we introduce the continuous multiresolution approximation (CMA) in terms of the continuous wavelet transform (CWT). Then we implement a fast algorithm to compute the CMA. We apply the CMA to a boundary to obtain approximations of the boundary at various resolutions. The CMA provides a consistent interpretation of objects with scale-variations. Moreover, we can quickly compute our representations by using the fast algorithm for the CMA. In the second part, we propose three representations for object recognition which cover most boundary-based object recognition problems. All three representations use the approximations obtained by the CMA. Each representation has different features and covers different types of matching problems but all representations are constructed by using curvature zero crossings of the approximations. Our representations provide a general but reliable solution to most boundary based object matching problems. Finally, we investigate the properties of our representations such as validity, efficiency, and reliability. We verified our results experimentally to demonstrate the feasibility of using our representations for object recognition.

A high performance architecture for real-time signal processing and matrix operations

The authors present the block data flow architecture (BDFA) which is an alternative to the systolic array and the wavefront array for locally recursive algorithms such as those used for digital signal processing, image processing, and matrix operations. The BDFA retains the advantageous features of a systolic array or a waveform array, such as regularity, modularity, and local interconnection. However, it uses a data partitioning strategy in addition to an algorithm partitioning strategy to reduce the data dependency, to decrease the interprocessor communication requirements and to decrease the hardware complexity compared to systolic and wavefront arrays. The BDFA also uses block data processing and the block data flow paradigm to minimize system management overhead due to communication protocols. Thus, the processors in a BDFA operate efficiently to achieve a system with a high throughput and a high efficiency.<<ETX>>

Parallel image processing with the block data parallel architecture

Many digital signal and image processing algorithms can be speeded up by executing them in parallel on multiple processors. The speed of parallel execution is limited by the need for communication and synchronization between processors. In this paper, we present a paradigm for parallel processing that we call the block data flow paradigm (BDFP). The goal of this paradigm is to reduce interprocessor communication and relax the synchronization requirements for such applications. We present the block data parallel architecture which implements this paradigm, and we present methods for mapping algorithms onto this architecture. We illustrate this methodology for several applications including two-dimensional (2-D) digital filters, the 2-D discrete cosine transform, QR decomposition of a matrix and Cholesky factorization of a matrix. We analyze the resulting system performance for these applications with regard to speedup and efficiency as the number of processors increases. Our results demonstrate that the block data parallel architecture is a flexible, high-performance solution for numerous digital signal and image processing algorithms.

Block realization of multidimensional IIR digital filters and its finite word effects

This paper describes the formulation and realization of multidimensional block systems and investigates their stability and numerical performance. The block system can be constructed by the concept of block shift invariance. It possesses the general property that if (\lambda_1,\lambda_2,\cdots,\lambda_N) is a pole of the original scalar system, then (\lambda^{L_1}_{1},\lambda^{L_2}_{2},\cdots,\lambda^{L_N}_{N} will be a pole of the block system, where L_i , is the block length in the i th tuple. Thus, a stable scalar system will guarantee that its extended block systems are stable. Two methods of deriving block transfer functions from a given scalar transfer function are proposed. Moreover, it is shown that the scalar transfer function can be derived from its extended block transfer function. Based on Givone-Roessers model, a unified approach of establishing 1-D to N -D block state-space models is presented. It is shown for the proposed block model that the dynamic range constraint in each tuple is invariant under block extension. In addition, the average roundoff noise variance due to the rounding errors in the i th tuple is reduced by a factor equal to the block length in this tuple when compared with its scalar counterpart.

Pipelined ALU for Signal Processing to Implement Interval Arithmetic

There are many applications within digital signal processing (DSP) that require the user to know how various numerical errors (uncertainty) affect the result. This uncertainty is represented by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are needed to implement interval arithmetic. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. We have proposed a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equivalent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed efficiently. This design has two independent modules operating in parallel to calculate the lower bound and upper bound of the output interval. The functional unit of the ALU performs the basic fixed-point interval arithmetic operations of addition, subtraction, multiplication and the interval set operations of union and intersection. In addition, the ALU is optimized to perform dot products through the multiply-accumulate instruction. Division traditionally is not implemented on digital signal processors unless computed with a shift operation. In this design, division by shifting is implemented. The ALU is designed to have maximum throughput while minimizing area

Automated Design Space Exploration for DSP Applications

We present a performance analysis framework that efficiently generates and analyzes hardware designs for computationally intensive signal processing applications. Our framework synthesizes designs from a high level of abstraction into well-constructed and recognizable hardware structures that perform well in terms of area, throughput and power dissipation. Cost functions provided by our framework allow the user to reduce the design space to a set of efficient hardware implementations that meet performance constraints. We utilize our framework to estimate hardware performance using a set of pre-synthesized mathematical cores which expedites the synthesis process by approximately 14 fold. This reduces the architectural generation and hardware synthesis process from days to several hours for complex designs. Our work aims at performing hardware optimizations at the architectural and arithmetic levels, relieving the user from manually describing the designs at the register transfer level and iteratively varying the hardware structures. We illustrate the efficiency and accuracy of our framework by generating finite impulse response filter structures used in several signal processing applications such as adaptive equalizers and quadrature mirror filters. The results show that hardware filter structures generated by our framework can achieve, on average, a 3 fold increase in power efficiency when compared to manually constructed designs.