Franc Brglez

Hardware-based weighted random pattern generation for boundary scan

The authors introduce WARP, a weighted test generation system that includes a canonical circuit for resolving weights to any desired precision. Either cellular automata registers (CARs) or linear feedback shift registers (LFSRs) are used as a source of random patterns, and optionally, it is possible to permute and linearly combine random bits from the source to control inputs to the weighting circuit. The authors analyze pattern coverage and conclude with benchmark results on fault coverage differences between CARs and LFSRs.<<ETX>>

A framework and method for hierarchical test generation

The authors have proposed and implemented a dynamic framework and a method for hierarchically generating test patterns from a hierarchical net list. They have shown consistent gains in CPU over the traditional gate-level implementation while maintaining identical levels of fault coverage. In generating and characterizing modules for a large and varied set of hierarchical benchmarks, the authors benefited considerably from the consistent representations that are available during synthesis from a high-level description or when modules are generated by a process of technology mapping into standard cells. The authors introduced the concept of a single generic module which is hierarchical; the traditional AND, OR, NAND, and NOR are included implicitly. They developed a module-oriented decision-making algorithm, MODEM, which entails a dynamic calculus and procedures such as implication, error propagation, line justification, and probabilistic testability measures for a single generic module. Without loss of generality they adapted the control flow and basic features of PODEM in the first implementation of MODEM.<<ETX>>

Corolla based circuit partitioning and resynthesis

This paper introduces a circuit partitioning method based on analysis of reconvergent fanout. We consider a DAG model for a circuit. We define a corolla as a set of overlapping reconvergent fanout regions. We partition the DAG into a set of non-overlapping corollas and use the corollas to resynthesize the circuit. We show that resynthesis of large benchmark circuits consistently reduces transistor pairs and layout area while improving delay and testability.

Automated synthesis for testability

The authors present an integrated, compiler-driven approach to digital chip design that automates mask layout and test-pattern generation for 100% stuck-at fault coverage. This approach is well suited for designs where it is most important the minimize the design cycle time rather than the silicon area. The authors show that by compiling from a unified design specification followed by logic synthesis it is possible to reduce the problem of automatic test-pattern generation. They present a language-based design capture and logic synthesis with hierarchical test pattern generation and redundancy removal techniques. A section on benchmark results highlights the close coupling of a language-based design specification, logic synthesis, and testability. >

Boundary scan with cellular-based built-in self-test

Boundary scan merging with built-in self-test is discussed. The proposed implementation of boundary scan represents a snapshot of the Joint Test Advisory Group Recommendation 1.0, while the built-in self-test implements the features of cellular automata. Test patterns generated from two distinct sources are examined, one with registers using cellular automata and the other, based on the conventional LFSR (linear-feedback shift register) configuration. Distinctive effects of these patterns on fault coverage of specific designs are analyzed and illustrated.<<ETX>>

CALLAS/OASIS: Combining Behavioral and Register-Transfer Synthesis Systems

While behavioral synthesis has still to prove its feasibility in an industrial environment, register-transfer level synthesis is already accepted. Especially, behavioral synthesis has to compete with state of the art register-transfer synthesis in terms of area and timing of the synthesized chips. We have performed several controlled benchmark experiments, using test examples and chip designs that range from 300 to 50,000 transistors. Our results demonstrate that behavioral synthesis can generate logic and layout with performance which is comparable to those produced from register-transfer descriptions provided by a designer.

Synergy of synthesis and test (logic design)

An integrated, compiler-driven approach to digital chip design that automates scan-based design and test pattern generation for 100% stuck at fault coverage is presented. The design process was partitioned into four major steps: compiler-driven unified structural/functional specification; logic synthesis that maps Boolean specifications into a net list of standard cells, scan-based test pattern generation; and fully automated standard cell layout. It has been shown that routine application of high-level design specification and logic synthesis can significantly reduce the problem of test pattern generation. The approach is especially well suited for designs where reducing design time is more important than minimizing silicon area. The components of the modular testability system are discussed with emphasis on hierarchical test pattern generation and redundancy removal techniques.<<ETX>>

Cellular Scan Revisited

In this paper, we re-examine the concept of test machine embedding and present a specific test machine architecture: cellular scan. This architecture offers advantages both over traditional scan as well as circular scan. Compared to traditional scan, cellular scan shortens required test time with vectors generated deterministically. Compared to circular scan, cellular scan requires less hardware, has no limitations on state coverage, and can significantly improve random pattern testability of sequential logic.