Clive Bittlestone

BEOL variability and impact on RC extraction

Historically, back end of line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.

Variation-aware analysis: savior of the nanometer era?

VLSI engineers have traditionally used a variety of CAD analysis tools (e.g. SPICE) to deal with variability. As we go into deep sub micron issues, the analysis is becoming harder due to many secondary effects becoming primary. Panelists will debate the variability trend and present the order of importance of many variability trends (Vdd, Vt, interconnect, Leff, gate width) and their impact on design tools and methodologies. What new design tools, new modeling methodologies, and new (or old) design styles will combine to address variability? Will conservative design to accommodate variability halt the progress of Moores law? Is life as we know it over, or are we facing an opportunity for innovation in tools and design that will move us forward over the barriers that technology has placed in our path?

Context analysis and validation of lithography induced systematic variations in 65nm designs

The impact of lithography-induced systematic variations on the parametric behavior of cells and chips designed on a TI 65nm process has been studied using software tools for silicon contour prediction, and design analysis from contours. Using model-based litho and etch simulation at different process conditions, contours were generated for the poly and active layers of standard cells in multiple contexts. Next, the extracted transistor-level SPICE netlists (with annotated changes in CD) were simulated for cell delay and leakage. The silicon contours predicted by the model-based litho tools were validated by comparing CDs of the simulated contours with SEM images. A comparative analysis of standard cells with relaxed design rules and restricted pitch design rules showed that restrictive design rules help reduce the variation from instance to instance of a given cell by as much as 15%, but at the expense of an area penalty. A full-chip variability analysis flow, including model-based lithography and etch simulation, captures the systematic variability effects on timing-critical paths and cells and allows for comparison of the variability of different cells and paths in the context of a real design.

Ultra low power design and future device interactions

We present the interactions between the process technology and the design that set the requirements for ultra low power and mixed signal circuits and chips that form the basis of the next generations of semiconductor applications.

Design and technology interaction beyond 32nm

This paper will discuss the challenges that continued technology scaling present to circuit designers and how the close interaction between the development of technology, design automation (EDA) tools and the circuit designer can overcome these challenges and enable designs that deliver the benefits customers expect from continued technology scaling.

Do Digital Design and Variability Mix like Oil and Water

Ever since process technology moved below 90nm, variability in manufacturing has been increasingly significant in the digital design flow; moving from a secondary issue to a primary design flow consideration. Initially addressed by performing verification under a couple process corners and later expanding to many corners and OCV, variability is adding excessive complexity to the digital design flow with uncertain benefit. For years analog designers have designed components considering the effects of variation, but this methodology has not been adapted to digital design. This panel seeks to address the question of whether or not variation can be dealt with in the digital design flow or whether the mind sets of digital design and design for variability are incompatible?

Design for manufacturing in the nanoscale era

Design for manufacturing, DFM, has been an increasingly important area for several years. Lithography at 90nm, 65nm, and below takes DFM into the critical zone for designers. Designers must now use extreme measures to achieve full technology entitlement of performance, power, area, reliability and yield. This presentations focus on major physical DFM effects and their impact on designers. It uses real life examples from 90 and 65nm to illustrate problems and trends. Several focus issues are linked to design impact and onto rules, modeling and other mitigation techniques. This talks touch on several critical areas such as RET/OPC/litho/etch, simulation, layout rules, and extraction. Both systematic and random effects are mentioned. Also covered are examples of some methods that are used to model or design around these issues to enable designers to meet technology entitlement goals.