Srinath Ramaswamy

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER) <10/sup -15/, transmit and receive equalization that can compensate up to 20 dB of channel loss is employed to remove intersymbol interference (ISI) resulting from finite channel bandwidth and reflections. The transmit feed-forward equalizer (FFE) uses a four-tap symbol-spaced programmable finite impulse response (FIR) filter followed by a 4-bit digital-to-analog converter (DAC) that drives a 50-/spl Omega/ transmission line. The receiver uses a half-baud-rate adaptive decision feedback equalizer (DFE) that cancels the first four symbol-spaced taps of postcursor ISI without use of speculative techniques. Both the transmitter and receiver use an LC-oscillator-based phase-locked loop (PLL) to provide low jitter clocks. Techniques to minimize the complexity of the FIR and DFE implementations are described. The transceiver is designed to be integrated in a standard ASIC flow in a 0.13-/spl mu/m digital CMOS technology. System measurements indicate the ability to transmit and recover data eyes that have been fully closed due to crosstalk and signal loss.

A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A BER<10/sup -15/ is measured over legacy backplane channels.

A High-Performance Digital-Input Class-D Amplifier with Direct Battery Connection in a 90nm Digital CMOS Process

The class-D amplifier system presented in this paper is a second-order architecture that operates on a digital PWM input and eliminates the use of an external carrier signal. It consists of two identical audio channels and a common section consisting of a PLL and a reference system. Each channel has a digital interpolation filter followed by a digital DeltaSigma modulator, PWM generator and two second-order analog loops.

A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS

This paper presents a 160 GHz center frequency pulsed 65 nm CMOS transceiver for short range radar applications. Four phased array transceivers were implemented in a single chip with antennas implemented in a BGA package. The implemented transmitter is capable of producing pulses of 100 ps widths ( >20 GHz RF bandwidth) at a 160 GHz carrier frequency. The measured effective isotropic radiated power (EIRP) is 18.8 dBm for continuous wave outputs. The analog beam forming receiver achieves an overall gain of 42.5 dB, -14 dBm IP1dB, 7 GHz bandwidth, and a noise figure of 22.5 dB. The sliding window time-dilation baseband relaxes the output data rate and subsequent digital processing requirements. Fine grained duty cycling reduces power dissipation. The entire chip consumes 2.2 W from 1.2/1.4 V supplies in a 65 nm digital CMOS process.

A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology

A backplane interconnect ASIC with 62 Gb/s full-duplex aggregate throughput uses 3.1 Gb/s serial link technology organized as 20 bidirectional channels to realize bandwidth. The chip operates with <5/spl times/10/sup 17/ aggregate BER and is fabricated in a 0.18 /spl mu/m CMOS technology, dissipating 9 W in a 768-pin flipchip BGA package.

A 1.5V 1mA 80dB passive /spl Sigma//spl Delta/ ADC in 0.13/spl mu/m digital CMOS process

A passive switched-capacitor /spl Sigma//spl Delta/ ADC consisting of only switches, capacitors and a comparator, is implemented in a 0.13/spl mu/m digital CMOS process. This high-speed low-voltage architecture is used in a zero-IF GSM transceiver and has a measured peak SNDR of 67dB over a bandwidth of 100kHz with a SFDR of 75dB and a dynamic range of 72dB. The ADC consumes 1mA from a 1.5V power supply at a clock rate of 104MHz.

A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitter

A low-power jitter tolerant 2nd order active-passive continuous-time sigma-delta ADC in 65nm CMOS is presented. The use of just one active Gm-C integrator and a feed-forward path from the ADCs input to the Gms output helps reduce power consumption. A FIR filter in the outermost feedback path reduces clock jitter impact. For a −2dBFS input, the ADC clocked at 300MHz achieves a 69dB SNR (10KHz – 1.2MHz BW) while consuming 1.16mW from a 1.4V supply.

Multi-modal smart bio-sensing SoC platform with >80dB SNR 35µA PPG RX chain

A multi-modal analog front end (AFE) and ultra-low energy bio-sensing CMOS SoC is presented. System/ circuit techniques enable signal path duty cycles as low as sub-1% and result in a 35μA Photo Plethysmography (PPG) RX Chain - 5X lower than published state of the art - while maintaining overall SNR > 80dBFS. The signal chain is adaptively synchronized by an ultra-low power FSM and includes a 1.3μW 14b 1kSPS SAR A/D. Input signal-aware, real-time data path adaptation is achieved by leveraging on-the-fly algorithms running on an external microcontroller (μC) to further reduce system energy. A programmable, asynchronous capacitive reset amplifier (PARCA) with NEF of 4.8 and dx/dt analog feature extractor demonstrate energy efficient ECG capture. A battery-powered, Bluetooth low energy (BLE) based, wearable platform with simultaneous ECG and PPG acquisition using this AFE has been demonstrated.

Low power ADC's for wireless communications

Recent advances in ADCs have enabled the development of low power receivers for wireless communication applications. In this paper we will discuss a specific class of ADCs, namely sigma delta ADCs. A brief overview of challenges in the design of these ADCs will be discussed along with the recent advances and techniques in overcoming these challenges. Two specific examples in the context of narrow and wide bandwidth systems will be discussed that demonstrate the viability of the recent techniques.

Programmable termination for CML I/O's in high speed CMOS transceivers

This paper describes I/O circuits that can be used in high-speed transceivers to communicate with next generation and legacy devices. We describe the transmitter and receiver front-end circuits that are designed to operate with dual termination voltage supplies. The receiver characterization, ESD protection and system level power up issues related to gate-oxide and electro-migration reliability are discussed.