Colin C. Murphy

Optimisation of the SHA-2 family of hash functions on FPGAs

Hash functions play an important role in modern cryptography. This paper investigates optimisation techniques that have recently been proposed in the literature. A new VLSI architecture for the SHA-256 and SHA-512 hash functions is presented, which combines two popular hardware optimisation techniques, namely pipelining and unrolling. The SHA processors are developed for implementation on FPGAs, thereby allowing rapid prototyping of several designs. Speed/area results from these processors are analysed and are shown to compare favourably with other FPGA-based implementations, achieving the fastest data throughputs in the literature to date

Differential power analysis of HMAC based on SHA-2, and countermeasures

The HMAC algorithm is widely used to provide authentication and message integrity to digital communications. However, if the HMAC algorithm is implemented in embedded hardware, it is vulnerable to side-channel attacks. In this paper, we describe a DPA attack strategy for the HMAC algorithm, based on the SHA-2 hash function family. Using an implementation on a commercial FPGA board, we show that such attacks are practical in reality. In addition, we present a masked implementation of the algorithm, which is designed to counteract first-order DPA attacks.

Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs

Security protocols are frequently accelerated by implementing the underlying cryptographic functions in reconfigurable hardware. However, unprotected hardware implementations are susceptible to side-channel attacks, and Differential Power Analysis (DPA) has been shown to be especially powerful. In this work, we evaluate and compare the effectiveness of common hiding countermeasures against DPA in FPGA-based designs, using the Whirlpool hash function as a case study. In particular, we develop a new design flow called Isolated WDDL (IWDDL). In contrast with previous works, IWDDL isolates the direct and complementary circuit paths, and also provides DPA resistance in the Hamming distance power model. The analysis is supported using actual implementation results.

Reducing Front-End Bandwidth May Improve Digital GNSS Receiver Performance

A novel evaluation of filtering and quantization losses for weak DS-CDMA receivers is presented. Using this method, joint optimization of filter center frequency and bandwidth is conducted for one-, two- and three-bit quantizers. It is demonstrated that a joint loss-analysis of these effects is necessary to optimize front-end design.

An Embedded Processor for a Pairing-Based Cryptosystem

In recent times bilinear pairings have been instrumental in the design of many new cryptographic protocols and have provided elegant solutions to existing protocol problems. The eta pairing is one such pairing and is an efficient computation technique based on a generalization of the Duursma Lee method for calculating the Tate pairing. The pairing can be computed very efficiently on genus 2 hyperelliptic curves. In this paper it is demonstrated that this pairing operation is well suited to a dedicated parallel hardware implementation on an FPGA. An eta pairing processor is described in detail and the architectures required for such a system are discussed. Prototype implementation results are presented over a base field of F2103 and the advantages of implementing the pairing on the dedicated processor are discussed

FPGA acceleration of the tate pairing in characteristic 2

This paper presents a dedicated hardware implementation of the cryptographic Tate pairing on an elliptic curve of characteristic 2 using theetaT method. Efficient techniques for pairing computation are discussed and optimised hardware architectures are presented. A hardware pipelining scheme is described, which provides a dramatic reduction in pairing computation time. A cryptographic processor for computation of the bilinear pairing is presented and implemented on an FPGA. It is demonstrated that an FPGA forms an ideal basis for pairing processor implementation due to ease of reconfigurability and the opportunity for rapid prototyping. Implementation results are provided for pairing calculation on an FPGA over the base field

Fast and Accurate Approximations for the Analysis of Energy Detection in Nakagami-m Channels

Previous research has identified several exact methods for the evaluation of the probability of detection for energy detectors operating on Nakagami-m faded channels. However, these methods rely on discrete summations of complicated functions, and so can take a prohibitively long time to evaluate. In this paper, three approximations for the probability of detection in Nakagami-m faded channels, having distinct regions of applicability, are derived. All have closed forms, and enable the fast and accurate computation of key performance metrics.

On the Convergence of the Chi Square and Noncentral Chi Square Distributions to the Normal Distribution

A simple and novel asymptotic bound for the maximum error resulting from the use of the central limit theorem to approximate the distribution of chi square and noncentral chi square random variables is derived. The bound enables the quick calculation of the number of degrees of freedom required to ensure a given approximation error, and is significantly tighter than bounds derived using the Berry-Esseen theorem. An application to widely-used approximations for the decision probabilities of energy detectors is also provided.

A simplified expression for the probability of error for binary multichannel communications

We present a simplified expression for the probability of error, Pe, for binary multichannel communications. The original expression was derived by Proakis in 1968. More recently, Simon and Alouini presented an expression involving the generalised Marcum Q-function. In this letter we present a simplified form of Simon and Alouinis expression. The application of this result to the calculation of performance metrics for communications over fading channels is also discussed.

Hardware architectures for the Tate pairing over GF(2m)

In this paper two different approaches to the design of a reconfigurable Tate pairing hardware accelerator are presented. The first uses macro components based on a large, fixed number of underlying Galois Field arithmetic units in parallel to minimise the computation time. The second is an area efficient approach based on a small, variable number of underlying components. Both architectures are prototyped on an FPGA. Timing results for each architecture with various different design parameters are presented.