Tim Kerins

Public-Key Cryptography for RFID-Tags

RFID-tags are a new generation of bar-codes with added functionality. An emerging application is the use of RFID-tags for anti-counterfeiting by embedding them into a product. Public-key cryptography (PKC) offers an attractive solution to the counterfeiting problem but whether a publickey cryptosystem can be implemented on an RFID tag or not remains unclear. In this paper, we investigate which PKC-based identification protocols are useful for these anti-counterfeiting applications. We also discuss the feasibility of identification protocols based on elliptic curve cryptography (ECC) and show that it is feasible on RFID tags. Finally, we compare different implementation options and explore the cost that side-channel attack countermeasures would have on such implementations

An FPGA implementation of a GF(p) ALU for encryption processors

Abstract Secure electronic and internet transactions require public key cryptosystems to establish and distribute shared secret information for use in the bulk encryption of data. For security reasons, key sizes are in the region of hundreds of bits. This makes cryptographic procedures slow in software. Hardware accelerators can perform the computationally intensive operations far quicker. Field-Programmable Gate Arrays are well-suited for this application due to their reconfigurability and versatility. Elliptic Curve Cryptosystems over GF( p ) have received very little attention to date due to the seemingly more attractive finite field GF(2 m ). However, we present a GF( p ) Arithmetic Logic Unit which can perform 160-bit arithmetic at clock speeds of up to 50 MHz.

Efficient hardware for the tate pairing calculation in characteristic three

In this paper the benefits of implementation of the Tate pairing computation on dedicated hardware are discussed. The main observation lies in the fact that arithmetic architectures in the extension field GF(36m) are good candidates for parallelization, leading to a similar calculation time in hardware as for operations over the base field GF(3m). Using this approach, an architecture for the hardware implementation of the Tate pairing calculation based on a modified Duursma-Lee algorithm is proposed.

Single-chip FPGA implementation of a cryptographic co-processor

A secure communications protocol contains a symmetric key cryptosystem, a hash algorithm and a method for providing digital signatures and key exchange using public key cryptography. This work presents an implementation of these core ciphers on a single FPGA. A novel architecture combining a symmetric-key and message authentication algorithm is proposed, with FIFO memory-blocks used as buffers to allow them run in parallel from the same data source. The generation of digital signatures and key exchange using a modular exponentiator core block is also considered. The complete design is implemented on a PCI prototyping card containing a Xilinx Virtex-2000E FPGA and SRAM memory banks. To optimise the data transfer rate between the SRAMs and the FPGA. The memory interface and encryption cores are partitioned into separate clock domains. Comparisons are then made between theoretical results from timing analysis reports and implemented results on the prototyping card.

Fully Parameterizable Elliptic Curve Cryptography Processor over GF(2)

In this paper we present an Elliptic Curve Point Multiplication processor over base fields GF(2m), suitable for use in a wide range of commercial cryptography applications. Our design operates in a polynomial basis is fully parameterizable in the irreducible polynomial and the chosen Elliptic Curve over any base Galois Field up to a given size. High performance is achieved by use of a dedicated Galois Field arithmetic coprocessor implemented on FPGA. The underlying FPGA architecture is used to increase calculation performance, taking advantage of the properties of this kind of programmable logic device to perform the large number of logical operations required. We discuss the performance of our processor for different Elliptic Curves and compare the results with recent implementations in terms of speed and security.

Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes

In this paper algorithms and architectures for new GF(3 m ) multiplier and inverter components are presented. It is described how they can be utilized as part of a hardware implementation of an Identity Based Encryption (IBE) scheme. The main computation, the Tate pairing in such a scheme in outlined and it is illustrated how it can be implemented on reconfigurable hardware using these components.

An Embedded Processor for a Pairing-Based Cryptosystem

In recent times bilinear pairings have been instrumental in the design of many new cryptographic protocols and have provided elegant solutions to existing protocol problems. The eta pairing is one such pairing and is an efficient computation technique based on a generalization of the Duursma Lee method for calculating the Tate pairing. The pairing can be computed very efficiently on genus 2 hyperelliptic curves. In this paper it is demonstrated that this pairing operation is well suited to a dedicated parallel hardware implementation on an FPGA. An eta pairing processor is described in detail and the architectures required for such a system are discussed. Prototype implementation results are presented over a base field of F2103 and the advantages of implementing the pairing on the dedicated processor are discussed

FPGA acceleration of the tate pairing in characteristic 2

This paper presents a dedicated hardware implementation of the cryptographic Tate pairing on an elliptic curve of characteristic 2 using theetaT method. Efficient techniques for pairing computation are discussed and optimised hardware architectures are presented. A hardware pipelining scheme is described, which provides a dramatic reduction in pairing computation time. A cryptographic processor for computation of the bilinear pairing is presented and implemented on an FPGA. It is demonstrated that an FPGA forms an ideal basis for pairing processor implementation due to ease of reconfigurability and the opportunity for rapid prototyping. Implementation results are provided for pairing calculation on an FPGA over the base field

FPGA implementation of a GF(2/sup 2M/) multiplier for use in pairing based cryptosystems

In this paper an architecture for GF(2/sup 4m/) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tale pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.

A flexible processor for the characteristic 3 η T pairing

The η T pairing is an efficient method for the calculation of the Tate pairing. In this paper, we describe the hardware implementation of the η T pairing on a supersingular elliptic curve of characteristic 3. All characteristic 3 operations required for the computation of the pairing are outlined in detail. We describe how the required extension field operations can be performed in terms of subfield operations, many of which can be computed in parallel in hardware. The hardware architectures required for pairing computation are also described. An efficient and reconfigurable processor utilising these hardware architectures is presented and discussed. The processor is highly reconfigurable and can easily be tailored for a low area implementation, or for a high throughput implementation or for a desired balance between the two. Results are provided for various configurations of the processor when implemented over the field F397 on an FPGA.