Colin Yates

Surface conditioning solutions to reduce resist line roughness

In this study, surface conditioning solutions were used during post-develop process to enhance the 193 nm lithography performance. These solutions were applied to the wafer surface in a surface treatment step between the DI water rinse and drying steps. Compared to the standard develop process, the formulated surface conditioning solution enabled a 24% reduction in line width roughness, particularly in the high frequency roughness components. The solution also improved the pattern collapse performance by enlarging the non-collapse window and extending the minimum CD feature size by 10 nm. Additional benefits provided by the formulated surface conditioner solution were minimal changes to CD and resist profile.

Deposition and Characterization of Polycrystalline Si1 − x Ge x Films for CMOS Transistors Gate Electrode Applications

Polycrystalline Si 1 - x Ge x (poly-SiGe) is a known gate electrode material that can mitigate poly-depletion effects, which exist in deep submicrometer complementary metal-oxide-semiconductor (CMOS) transistors, due to its lower dopant activation temperatures and smaller bandgaps. As an important step toward the manufacturing of poly-SiGe electrode-based CMOS transistors with enhanced performances, this study focuses on the deposition of poly-SiGe films with different structural features and the characterization of the physical properties of these films. The electrical performance and the reduction in poly-depletion effects of the poly-SiGe electrodes in capacitors fabricated using these films were verified using capacitance-voltage measurements.

Characterization of e-beam induced resist slimming using etched feature measurements

ArF resist is critical in the production of todays state-of-the-art lithography. It is well documented that process control measurements via CD-SEM at landing energies greater than 200 eV significantly slims the ArF resist, leading to inaccurate measurements and changes in the final geometries of the feature measured in-circuit. Resist slimming is most frequently quantified as the difference between consecutive measurements of the same feature. This study uses an alternative method to measure the slimming caused by a single measurement on a resist feature. Measurements were taken of etched features that had been exposed on a CD-SEM to various beam conditions prior to etch. The slimming was calculated by measuring the delta between the exposed portion of the line and the adjacent un-exposed portion of the same line. Previous work and the results of this current work show that the slimming of the ArF resist carries over through the etch process and measurably altered the final CD. In this work a systematic study of various image acquisition conditions shows that the choice of landing energy dominates all other factors affecting the amount of slimming, with near zero slimming measured for the 100 eV landing energy.

Application of critical shape metrology to 90nm process

Critical Shape Metrology (CSM), a Monte-Carlo simulation-based technique that extracts feature shape information from top-down CD-SEM images, is applied to study advanced process steps of etched polysilicon layers. True bottom CDs and sidewall angles are among the parameters obtained during real-time wafer inspection. Comparison is made to FIB cross-sections obtained independently from select test sites.