Ebo H. Croffie

Application of rigorous electromagnetic simulation to SLM-based maskless lithography for 65-nm node

Maskless lithography imaging based on SLM tilt mirror architecture requires illumination of light on a non-planar reflective topography. While the actual mirror dimensions can be much larger than the wavelength of light, the spacing between mirrors and the tilt range of interest are on the order of the wavelength. Thus, rigorous electromagnetic solution is required to capture light scattering effects due to the non-planar topography. We combine high NA imaging simulation with rigorous simulation of light scattering from the mirrors to study its effects on 65nm maskless lithography imaging. We vary mirror size, mirror tilt arrangemetn, feature type and illumination settings and compare the rigorous light scattering imagign resutls wtih standard imaging simulations using Kirchoff approximation. While electromagnetic scattering effects are present in the form of lateral standing waves and edge streamers in reflected light near-field intensity, they have negligible effects on SLM imaging for mirror sizes more than 1μm2. The effects of mirror tilt arrangement on diffraction orders aer used to study the through-focus behavior of alternating rows arrangement used in the SIGMA maskwriters as well as alternative arrangements. The good imaging properties of the alternating rows arrangement used in the SIGMA maskwriters as well as alternative arrangements. The good imaging properties of the alternating rows arrangement are confirmed and a multipass overlay scheme giving further image fidelity improvements is suggested.

Strong phase-shifting optical maskless lithography for the 65 nm node and beyond

Ever-increasing reticle cost makes optical maskless lithography an attractive alternative to mask-based technologies, particularly for low-volume runs such as prototypes, ASIC personalization, and engineering short loops. If the resolution and imaging performance of the optical maskless exposure tool can match or exceed standard reticle based scanners, then one can seamlessly integrate mix-and-match strategies into the manufacturing flow or even go to an all maskless strategy since resists and film stacks are unchanged. We have developed optical maskless analogs for a majority of the reticle based strong phase shifting techniques. These include analogs to binary, attenuated PSM, alternating PSM, CPL + assist features, and vortex reticles. We will present simulation of maskless vs. reticle based lithography of all these techniques, demonstrating how to move off grid, change CD, OPC correct through pitch, and present common feature process windows and CD / image placement error sensitivities that suggest that for certain applications, optical maskless will be superior to reticle based lithography.

Fast resist modeling and its application in 193-nm lithography

A new resist threshold model based on image behaviors on directions parallel as well as normal to feature edges has been developed for predicting critical dimensions (CD) of two-dimension patterns. In this new model (2D-RTM), resist threshold is assumed as a second-order polynomial function of five image parameters that consist of image intensity and slope. Extensive verifications of 2D-RTM have been done by using both rigorous resist models and experimental measurements. 2D-RTM is found to be a good approximation of rigorous model within certain range of dose and defocus variation. For 130nm technology in LSI Logic, 2D-RTM improves CD prediction accuracy for typical 2D patterns to a maximum error of 3.1nm and average of 1.21nm, which gives an improvement of a factor of two compared with conventional resist threshold model.

Electrical validation of resolution enhancement techniques

A number of techniques are used for resolution enhancement in leading edge lithography. As feature dimensions shrink, these resolution enhancement techniques (RETs) become more aggressive, causing huge increases in data volume, complexity and write time. The results of these techniques are verified using methods such as SEM measurements of resist or etched structures on the wafer. These RETs tend to either over or under-compensate by way of the suggested corrections or enhancements with respect to the actual device operation. In addition, the systematic and random metrology errors inherent in wafer level top-down SEM measurements become more significant as feature sizes shrink and tolerances become tighter. These errors further cloud the decision as to which RET is most suitable and necessary. To overcome these problems, we have designed an electrical test vehicle which targets those geometries most prevalent in the cells for a given technology. Electrical test (E-test) structures are then varied around these geometries covering the design rule space. Device parameters are measured over this design space for various RETs. This method reconciles the accuracy or effectiveness of RET models using electrical device parameters and uses the same to choose the RET which results in the lowest NRE while at the same time meeting all electrical requirements.

Manufacturing of ArF chromeless hard shifter for 65-nm technology

For logic design, Chrome-less Phase Shift Mask is one of the possible solutions for defining small geometry with low MEF (mask enhancement factor) for the 65nm node. There have been lots of dedicated studies on the PCO (Phase Chrome Off-axis) mask technology and several design approaches have been proposed including grating background, chrome patches (or chrome shield) for applying PCO on line/space and contact pattern. In this paper, we studied the feasibility of grating design for line and contact pattern. The design of the grating pattern was provided from the EM simulation software (TEMPEST) and the aerial image simulation software. AIMS measurements with high NA annular illumination were done. Resist images were taken on designed pattern in different focus. Simulations, AIMS are compared to verify the consistency of the process with wafer printed performance.

Analysis of off-axis-illumination-based phase-edge/chromeless mask technologies

Production readiness of phase-edge/chromeless reticles employing off-axis illuminations for 65nm node lithography is assessed through evaluation of mask design conversion and critical layer lithography performance. Using ASML /1100ArF scanners, we achieved k1=0.33 for chromeless phase shift mask (crlPSM) with more than 0.6um DOF for dense features. Subresolution assist features allow for acceptable depth of focus through pitch. However, chromeless feature linearity fall-off continues to be a major issue hampering the acceptance of crlPSM for production. Several mask data conversion schemes such as chromeless gratings and chrome patches have been proposed as viable solutions to mitigate the chromeless linearity fall-off issue. We evaluated chromeless gratings, chromeless rims and chrome patches and report on their performance in resolving the chromeless linearity fall-off issues as well as mask process complexity associated with each solution.

Statistical analysis of poly line printability affected by sPSM manufacturing errors

LSI Logics OPC package, Molotof, integrated into several RET flows has been successfully applied for strong phase shift mask simulation and optimization. Molotof simulator was used to predict sPSM imaging performance in response to statistical errors of alternating phase shift reticle manufacturing. Mask manufacturing errors were reproduced by generating a virtual gds mask with random values of sPSM control parameters such as phase depth, phase width and phase intensity. By measuring critical dimensions and image placement errors of a simulated aerial image for each random event, the image printability performance was calculated. The approach allows for quantitative evaluation and optimization of a strong PSM manufacturing specification by analyzing the distributions of critical dimensions and image placement errors. 2D-model, metrology and simulation flow for performing statistical analysis are discussed. Sensitivity to a single parameter variation and full statistical analysis of the 90nm poly line imaging performance affected by manufacturing errors is presented. The optimum range of phase depth, phase width and phase intensity, yielded 100% of critical dimensions and image placement errors, complying with 90nm technology design rules was found in simulation. Simulation results are confirmed by empirical data.

Sensitivity of the 65-nm poly line printability to sPSM manufacturing errors

A methodology and a Monte Carlo simulation flow with integrated LSI Logics OPC package, Molotof, was applied to the 65nm poly line sensitivity analysis. Strong phase shift mask (sPSM) manufacturing specifications were optimized to obtain image critical dimensions (CD) and image placement errors (IPE) complying with technology design rules. Reticle manufacturing statistical errors of phase depth, phase width, and phase intensity imbalance were used to generate a virtual sPSM for imaging poly lines. A criterion for qualifying reticle specification is to obtain all latent image CDs and IPEs within a design rule allowed range for a given mask specification. The approach allows for computing reticle and litho budgets into CD imaging performance. We present simulation and empirical results of statistical analysis of the 65nm poly line (clear field) printability, and a method for optimizing a strong phase shift reticle specification. Sensitivity to a single parameter variation and full statistical analysis of the 65nm poly line imaging performance affected by manufacturing errors is presented. The optimum reticle specification, yielded 100% of critical dimensions and image placement errors, was found in simulation and confirmed by empirical data.

Analysis of etched quartz solutions for 65-nm node critical layer lithography

Manufacturability and economical viability of etched quartz solutions for 65nm node critical layer lithography is assessed through evaluation of mask technology conversion complexity, mask process complexity, wafer processing cost and SRAM cell critical layer lithography performance. The etched quartz technologies under consideration are the full-layout alternating phase shift mask solution (FullPhase altPSM) and chromeless hard shifter phase shift mask solution (crlPSM). Using 0.63 NA exposures, we achieve k1 =0.29 (DOF=0.6um) and k1 =0.33 (DOF=0.8um) for altPSM and crlPSM, respectively. 60nm isolated feature DOF is more than 0.8um for altPSM. The crlPSM isolated feature DOF without sub resolution assist features is about 0.3um. Simulations results of crlPSM isolated features with sub resolution assist features using NA=0.75 show that DOF of 0.3um is attainable for crlPSM. Experimental results are used to calibrate wafer volume cross over model for these competing technologies with specific focus on die size, k1 and DOF related yield as wafer processing cost drivers. Results show that altPSM has lower wafer processing cost due to better lithography yield at smaller die sizes. Thus, though the mask set of altPSM solution is more expensive than crlPSM, the altPSM solution is more economical for high volume production of 65nm node technologies. The wafer volume crossover model allows for the most cost effective mask solution to be employed for a given logic device and wafer volume expectation.