Colleen H. Ellenwood

Voltage-dividing potentiometer enhancements for high-precision feature placement metrology

Improvements to the design of a modified voltage-dividing potentiometer permit the measurement of the center-to-center separations of parallel features with residual errors well below 10 nm. The modified test structure offers fabrication robustness and a range of application advantages over alternative approaches. In earlier work describing this test structure, the measurements reported were offset by a substrate-dependent error attributed by modeling to certain imperfections in the replication of the inside corners of the intersection of voltage taps with the bridge of the test structure. The work described provides experimental confirmation of the model, and two alternative modified designs that eliminate the source of the error are presented. Measurements from all four designs demonstrated that the two modified configurations eliminated the substrate pattern replication errors to which the original design was vulnerable. The end result is a robust feature-placement metrology tool.<<ETX>>

Test structure for the in-plane locations of project features with nanometer-level accuracy traceable to a coordinate measurement system

A new test structure is reported. It is designed to measure the positions of the images of an array of features projected from a mask into a resist film on substrate with accuracy better than 10 nm. The resist film on the substrate covers a nominally matching array of partially formed versions of the test structure prepatterned in a conducting film. Instances of the finished structure are formed on the substrate by further selective removal of conducting material from the partially formed test structures where they are overlaid by images of the fiducial marks on the mask. At each array point, the feature of the completed test structure that is defined by the overlay of the image of the fiducial marks on the mask is called the pointer. The part of the partially formed test structure that is unaffected by the overlay of the images of the fiducial marks on the mask serves as a ruler. Electrical testing accurately provides the precise location of the pointer relative to the ruler within each test structure. The locations of the rulers prepatterned on the substrate are determined with a coordinate measurement system (CMS) called the NIST (National Institute of Standards and Technology) Molecular Measuring Machine (M-Cubed).<<ETX>>

Characterization of SiC PiN diode forward bias degradation

An automated test system is developed and utilized to electrically monitor the emitter, base, and end region excess carrier lifetimes at periodic intervals during the forward bias stress of SiC PiN power diodes. The test system uses a specialized diode switching circuit, computer-controlled instrumentation, and model parameter extraction software. This lifetime measurement method is used to monitor diodes with degradation times ranging from one minute to over several hundred hours, and diodes that do not degrade. Diodes made from 11-20 crystal orientation material are also measured to examine the effects of stacking fault growth direction. Light emission studies are used to monitor the growth of stacking faults during the degradation. The results indicate that stacking fault growth and on-state voltage degradation are strongly correlated with a decrease in diode stored charge density and stored charge decay rate resulting from a reduction in effective end region lifetime and/or reduction in device conduction area. Degradation results from various crystal orientation devices indicate that a barrier to current traversing the plane of the stacking fault is primarily responsible for the change in electrical properties.

A novel method for fabricating CD reference materials with 100 nm linewidths

A technique has been developed to fabricate 100-nm critical dimension (CD) reference features with i-line lithography by utilizing a unique characteristic of single-crystal silicon-on-insulator films: under certain etch conditions, the edges of features align to crystallographic surfaces. In this paper we describe this technique, show results of the process, and present electrical CD measurements that support the use of this technique for producing current and future generations of reference materials for the semiconductor industry.

Electrical Test Structure for Overlay Metrology Referenced to Absolute Length Standards

This test structure is based on the voltage-dividing potentiometer principle and was originally replicated in a single lithography cycle to evaluate feature placement by a primary pattern generator. A new test structure has now been developed from the single-cycle version and has been used for measuring the overlay of features defined by two different exposures with a stepping projection aligner. The as-measured overlay values are processed by an algorithm that minimizes the effects of nominal random pattern imperfections. The algorithm further partitions measurements of overlay into contributions that derive, respectively, from misregistration of the image fields projected by the two masks and from the drawn misplacement of features on the masks. The numerical estimates of these contributions so obtained from the electrical measurements were compared with those extracted from the same features by the NIST line scale interferometer, providing traceability to absolute length standards. The two sets of measurements were found to agree to within the several-nanometer uncertainty cited for the line scale interferometers readings alone.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Test chip for the evaluation of surface-diffusion phenomena in sputtered aluminum planarization processes

A test chip has been designed and fabricated for the evaluation of surface-diffusion phenomena. It allows the confirmation of the correct sample cross-section bevel angle and orientation for scanning electron microscope (SEM) inspection of step coverage. These features eliminate ambiguities that may otherwise arise in the interpretation of the SEM images. The chip design provides arrays of vias with multiple combinations of size and spacing to enable characterization and modeling of the aluminum planarization phenomena for a full range of deposition parameters. It also incorporates electrically readable test structures that allow relating the SEM images of step coverage to corresponding electrical properties, such as electromigration, of the deposited metal. The overall objective is to permit the selection of deposition parameters that simultaneously produce visually acceptable step-coverage images and optimized electrical properties of the film.<<ETX>>