Loren W. Linholm

Recent Developments in Electrical Linewidth and Overlay Metrology for Integrated Circuit Fabrication Processes

Electrical linewidth measurements have been extracted from test structures replicated in planar films of monocrystalline silicon that were electrically insulated from the bulk-silicon substrate by a layer of silicon dioxide formed by separation by the implantation of oxygen (SIMOX) processing. Appropriate selection of the surface orientation of the starting material, the design and orientation of the structures features, and patterning by a lattice-plane selective etch provide features with planar, atomically smooth sidewalls and rectangular cross sections. The primary motivation for this approach is to attempt to overcome the serious challenge posed by methods divergence to the certification of linewidth reference-materials for critical-dimension (CD) instrument calibration and related tasks. To enhance the physical robustness of reference features with deep submicrometer linewidths, the new test structure embodies short reference-segment lengths and arbitrarily wide voltage taps. Facilities for reconciliation of measurements extracted from the same feature by all normally practiced techniques are also implemented. In overlay metrology, electrical inspection of two types of hybrid overlay targets allows pixel calibration of, and shift extraction from, the overlay instruments. The overall strategic focus of this research is to resolve methods-divergence issues and possibly to develop universal deep-submicrometer linewidth reference materials for CD instruments and techniques for instrument- and process-specific shift extraction for optical overlay metrology.

Test structures for referencing electrical linewidth measurements to silicon lattice parameters using HRTEM

A technique has been developed to determine the linewidths of the features of a prototype reference material for the calibration of critical-dimension (CD) metrology instruments. The reference features are fabricated in mono-crystalline-silicon with the sidewalls aligned to the (111) lattice planes. A two-step measurement procedure is used to determine the CDs. The primary measurement is via lattice-plane counting of selected samples using high-resolution transmission electron microscopy (HRTEM); the transfer calibration is via electrical CD (ECD) test-structure metrology. Samples of these prototype reference materials were measured and provided, as the National Institute of Standards and Technology (NIST) Reference Material RM8110, to International SEMATECH for evaluation by its member companies. In this paper, we will describe the measurement procedure and show how the combined uncertainty of less than 15 nm was derived. Additionally, we demonstrate a technique to automate the analysis of the phase-contrast images in order to both minimize the cost and reduce the uncertainty of the calibration of the standards.

High-resolution transmission electron microscopy calibration of critical dimension (CD) reference materials

The National Institute of Standards and Technology and Sandia National Laboratories have developed a procedure for producing and calibrating critical dimension (CD), or linewidth, reference materials. These reference materials will be used to calibrate metrology instruments used in semiconductor manufacturing. The reference features, with widths down to 100 nm, are produced in monocrystalline silicon with all feature edges aligned to specific crystal planes. A two-part calibration of these linewidths is used: the primary calibration, with accuracy to within a few lattice plane thicknesses, is accomplished by counting the lattice planes across the sample as-imaged through use of high-resolution transmission electron microscopy. The secondary calibration is the high-precision electrical CD technique. In this paper, we describe the calibration procedure for these reference materials and estimate the related uncertainties.

A modified sliding wire potentiometer test structure for mapping nanometer-level distances

Present a modified voltage-dividing potentiometer test structure which overcomes a problem typical in scaling electrical test structures: it provides a correction for electrical length shortening of a resistor strip caused by the attachment of voltage taps of nonnegligible width. The test structure was implemented in chrome on quartz, and measurements of displacements between 10 and 500 nm with +or-12-nm random error were made using available test equipment. The enhanced precision of the measurement derives from reducing the size of the structure from previous design methods. The enhanced accuracy of the displacement measurement derives from scaling the length of the potentiometer bridge while simultaneously providing for nonscaled widths of the voltage taps. Measurements using these corrections demonstrate an improvement of up to 20% in measurement accuracy, and further improvements can be expected with optimized designs.<<ETX>>

Comparisons of measured linewidths of submicrometer lines using optical, electrical, and SEM metrologies

An investigation is being carried out to determine the ability of three methods of linewidth metrology to measure the dimensions of features of less than 0.5 micrometers . The three methods are transmitted-light optical microscopy, electrical test structure, and scanning electron microscopy (SEM). To permit the inclusion of transmitted-light optical microscopy in this investigation, 100-nm thick Ti films were patterned using normal VLSI processing techniques on a 150-mm diameter quartz wafer. The cross-bridge resistor test structure was used since this structure has been widely used in industry and it allows the results from all three metrological techniques to be compared. The design bridge widths of the test structures range from 0.4 micrometers to 1.0 micrometers . The results of these measurements show systematic and uniform offsets between the different techniques. In this paper we discuss the different techniques and describe the observed results.

Comparison of properties of electrical test structures patterned in BESOI and SIMOX films for CD reference-material applications

The National Institute of Standards and Technology (NIST) is exploring the feasibility of using artifacts fabricated on silicon-on-insulator (SOI) materials to quantify methods divergence, for critical dimension (CD) metrology applications. Test structures, patterned on two types of (110) SOI materials, SIMOX (Separation by IMplantation of OXygen) and BESOI (Bonded-and-Etched-back Silicon-on-Insulator), have been compared. In this paper, we describe results of electrical critical dimension (ECD) measurements and the relative performance of the test structures fabricated on the two SOI materials.

A machine-learning classification approach for IC manufacturing control based on test structure measurements

A machine-learning method is presented for classifying electrical measurement results from a custom-designed test chip. These techniques are used for characterizing the performance of a 1- mu m integrated circuit lithography process. Emphasis is on the development of a method for producing reliable classification rules from databases containing large samples of measurement data. The algorithm used is the Iterative Dichotomiser version 3, or ID3, originally developed by J.R. Quinlan (1983). The resultant classification rules are implemented in an expert-system shell. This combination provides a means of training and customizing a diagnostic system to be responsive to process variations experienced in a semiconductor manufacturing environment. Descriptions are given of the test chip, data-handling methods, rule-generation techniques, and statistical data reduction and parameter-extraction techniques used. An analysis of error introduced by noise in the rule formation process is presented. >

Reference-length shortening by Kelvin voltage taps in linewidth test structures replicated in monocrystalline silicon films

Electrical test structures replicated in thin films of mono-crystalline silicon offer potential benefits as physical standards for linewidth and overlay metrology. When the test structures features, the lattice of the monocrystalline film, and the surface plane of the film have particular mutual orientations, the junctions of the Kelvin voltage taps with the bridge feature of the test structure have three-dimensional geometries which can be specified by four well-defined dimensional parameters. Since the voltage-tap and bridge linewidths determine the magnitude of the voltage-tap-induced electrical bridge-length-shortening effect, measurement of the latter offers an additional means for validating measurements of the linewidth of the bridge feature. This paper reports the results of simulations of current-flow through voltage-tap-to-bridge junctions, thus providing values of the expected voltage-tap-induced electrical bridge-length-shortening effect for a particular application. In addition, the calculated values are compared with experimental measurements. A parametric representation of the effective voltage-tap-induced electrical bridge-length-shortening as a function of voltage-tap and bridge linewidths has been developed. Its purpose is to facilitate a rapid independent estimation of the values of the shortening effect generated during electrical linewidth and overlay measurements performed on test structures replicated in thin films of mono-crystalline silicon.

Voltage-dividing potentiometer enhancements for high-precision feature placement metrology

Improvements to the design of a modified voltage-dividing potentiometer permit the measurement of the center-to-center separations of parallel features with residual errors well below 10 nm. The modified test structure offers fabrication robustness and a range of application advantages over alternative approaches. In earlier work describing this test structure, the measurements reported were offset by a substrate-dependent error attributed by modeling to certain imperfections in the replication of the inside corners of the intersection of voltage taps with the bridge of the test structure. The work described provides experimental confirmation of the model, and two alternative modified designs that eliminate the source of the error are presented. Measurements from all four designs demonstrated that the two modified configurations eliminated the substrate pattern replication errors to which the original design was vulnerable. The end result is a robust feature-placement metrology tool.<<ETX>>

The enhanced voltage-dividing potentiometer for high-precision feature placement metrology

Enhancements to the voltage-dividing potentiometer, an electrical test structure for measuring the spatial separations of pairs of conducting features, are presented and discussed. These enhancements reduce or eliminate systematic errors which can otherwise lead to uncertainties as large as several hundred nanometers. These systematic errors, attributed by modeling to asymmetries at certain intersections of conducting features in the test structure, are eliminated by modifications to the test structure and test procedures.