Come Rozon

UDSM subthreshold leakage model for NMOS transistor stacks

In this paper, a new, analytical model for subthreshold leakage estimation in the ultra deep submicron (UDSM) realm is proposed. Most previous attempts at subthreshold leakage estimation in transistor stacks are not tailored for the UDSM realm and are based on either a look up table approach, and/or assume that all the transistors in the stack have a fixed width. The analytical estimation model proposed in this paper is capable of estimating subthreshold leakage in UDSM NMOS transistor stacks with different transistor widths. The model achieves this by estimating the stack nodal voltages. In this paper, transistor stacks of two, three and four transistors are considered. Compared to SPICE simulations using PTMs BSIM4 models, our analytical model achieved an average error of 8.1% for the one, two, three and four transistor stacks for 65, 45 and 32nm CMOS process technologies. The model also exhibits significant runtime savings when compared with SPICE.

Accurate Total Static Leakage Current Estimation in Transistor Stacks

In this paper, a simple model for the estimation of static leakage current in NMOS transistor stacks is introduced. The three leakage mechanisms addressed are subthreshold leakage, gate-tunneling and gate induced drain leakage (GIDL). The algorithmic description of the model can be broken down into three phases i) pre-extraction , ii) estimation and iii) width scaling. In the pre-extraction phase, data necessary for subthreshold leakage estimation is extracted a priori. This also involves characterizing voltages required for a specific set of input vector scenarios (exception vectors/voltages). In the estimation phase, unit width GIDL and gate tunneling are estimated deterministically while subthreshold leakage is estimated using the pre-extracted data. Finally, in the width scaling phase each leakage component is then width scaled and summed, to give the total static leakage exhibited by the stack. The proposed model was scripted in MatLab and compared with SPICE simulations for various scenarios. The average total error for each scenario was under 3%.

A new subthreshold leakage model for NMOS transistor stacks

In this paper, a new model for subthreshold leakage estimation in the UDSM realm is proposed. This model is able to estimate subthreshold leakage in transistor stacks with varying transistor widths. Although only transistor stacks of 2 and 3 transistors are considered, the model can be easily expanded to deal with 4 and 5 transistor stacks. The model achieves this by estimating the stack nodal voltages. Compared to SPICE simulations, the model lead to 3% and 10% average error for the two and three transistor stacks respectively in the 45nm Predictive Technology Model (PTM) process. Slightly lower errors were achieved in the 65nm PTM process.

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Popular generic fault models, which exhibit limited realism for different IC technologies, have been widely misused due to their simplicity and cost-effective implementation. This paper introduces a system for deriving accurate, technology specific fault models that are based on analog defect simulation. This technique, though used in other research efforts, is formally defined in this paper and a systematic approach is developed. It is supported by a new software tool that provides a push-button solution for the previously tedious task of obtaining accurate ASIC cell defect to fault mappings. Furthermore, upon completion of the cell defect analysis, the tool automatically generates VITAL compliant, defect-injectable, VHDL cell models.

Comprehensive defect analysis and defect coverage of CMOS circuits

In this paper we present a methodology to perform defect analysis of digital CMOS circuits using comprehensive transistor macro defect models. These models are based on eighteen defects, hard and soft, for each MOS transistor. Defects are activated individually and circuits are exhaustively simulated to determine the responses, which are then compared with that of gold circuits. Both defect and fault coverages are determined including statistics to determine the effectiveness of a testing method. Results on combined testing and implications on incremental fault coverages are presented.

Testability analysis and fault modeling of BiCMOS circuits

Defect models have been used for testability analysis of BiCMOS circuits and the results have been compared with an analysis of CMOS circuits. Using a nominal point approach, faults generated are classified as logical or performance degradation faults. It is found that logical fault testing can only cover a small percentage of the total fault set, 54% for BiCMOS, versus 69% for equivalent CMOS gates. Delay faults and current faults are analyzed as applied to BiCMOS and CMOS gates. It is shown that logical fault testing in conjunction with either delay fault testing or current fault testing promises the highest fault coverage for BiCMOS logic gates, around 95%.

Accurate CMOS bridge fault modeling with neural network-based VHDL saboteurs

This paper presents a new bridge fault model that is based on a multiple layer feedforward neural network and implemented within the framework of a VHDL saboteur cell. Empirical evidence and experimental results show that it satisfies a prescribed set of bridge fault model criteria better than existing approaches. The new model computes exact bridged node voltages and propagation delay times with due attention to surrounding circuit elements. This is significant since, with the exception of full analog simulation, no other technique attempts to model the delay effects of bridge defects. Yet, compared to these analog simulations, the new approach is orders of magnitude faster and achieves reasonable accuracy; computing bridged node voltages with an average error near 0.006 volts and propagation delay times with an average error near 14 ps.

Optimized distributed processing of scaling factor in CORDIC

CORDIC is a well known iterative algorithm used to evaluate various transcendental functions. There have been a number of papers describing various ways of speeding up this algorithm. One of the performance bottlenecks of CORDIC is the requirement to multiply the results of the x and y data path by a constant scaling factor. Depending on the architecture, such solutions might not necessarily provide added benefits. In this paper, processing of the scaling factor is applied in a distributed way in order to achieve maximum efficiency for both pipelined and recursive architectures.

IC bridge fault modeling for IP blocks using neural network-based VHDL saboteurs

This paper presents a new bridge fault model, suitable for IP blocks, that is based on a multiple layer feedforward neural network and implemented within the framework of a VHDL saboteur cell. Empirical evidence and experimental results show that it satisfies a prescribed set of bridge fault model criteria better than any existing approach. The new model computes bridged node voltages and propagation delay times with due attention to surrounding circuit elements. This is especially significant since, with the exception of full analog defect simulation, no other technique even attempts to model the delay effects of bridge defects. Yet, compared to these analog simulations, the new approach is several orders of magnitude faster and, for a 0.35u cell library, is able to compute bridged node voltages with an average error near 0.006 volts and propagation delay times with an average error near 14 ps. Furthermore, dealing with a concept that has not previously been considered in related research, the new model is validated with respect to deep-submicron technologies for limited gate-count circuit modules.

Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models

This paper introduces a methodology for assessing the fault security attributes of Fault Secure (FS) circuits. Structural VHDL circuit descriptions are used to simulate the fault effects of reafistic transistor level defects that occur in CMOS ICs. Defective standard cells are simulated at the analog level of abstraction and the resultant fault effects are implemented in defect-injectable VHDL models to allow logic simulation. Typical fault effects include functional changes, propagation delay increases, sequential logic faults, stuck-at faults, reduced noise margins, and increased IDDQ. The defect-injectable VHDL models are swapped into FS circuit designs and the effects of the defects are analyzed in the context of the digital circuit. The FS circuits can then be assigned a figure of merit based on the ratio of detected defects to those that actually cause output errors. To facilitate the execution of the methodology, an integrated software tool has been developed that, in combination with a commercial VHDL simulation tool, provides an automated means for determining the figure of merit. Implemented using a GUI, the new tool is user friendly and flexible enough to be used with various logic circuits and different IC technologies. Three different checker, as benchmarks, were evaluated to demonstrate the FSA tool and the methodology to assess their relative fault security.