Congbing Li

Analog/mixed-signal circuit design in nano CMOS era

This paper describes analog/mixed-signal circuit design in the nano CMOS era. Digitally-assisted analog technology is becoming more important, and as an example, our fully digital FPGA implementation of a TDC with self-calibration is shown. Since pure analog circuits are still present and “good” device modeling is required for their designs, device modeling technology for nano CMOS with complicated behavior is also reviewed.

Experimental verification of timing measurement circuit with self-calibration

This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC using a Programmable System-on-Chip (PSoC), and measurement results show that TDC linearity is improved by the self-calibration. All TDC circuits, as well as the self-calibration circuits can be implemented as digital circuits, even by using FPGA instead of full custom ICs, so this is ideal for fine CMOS implementation with short design time.

A gray code based time-to-digital converter architecture and its FPGA implementation

A glitch-free time-to-digital converter (TDC) based on Gray code is presented. This architecture can reduce hardware, power consumption, as well as chip area significantly compared to a flash type TDC, while keeping comparable performance and glitch-free characteristics. Its proof-of-concept prototype was implemented on FPGA, and the measurement and simulation results validate the effectiveness of the proposed architecture.

Time-to-digital converter architecture with residue arithmetic and its FPGA implementation

This paper describes a time-to-digital converter (TDC) architecuture with residue arithmetic or Chinese Remainder theorem. It can reduce the hardware and power significantly compared to a flash type TDC while keeping comparable performance. Its FPGA implementation and measurement resuts show the effectiveness of our proposed architecture.

A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator

This paper proposes a small chip area stochastic calibration for TDC linearity and input range, and analyzes it with FPGA. The proposed calibration estimates the absolute values of the delay of the buffers and the range of measurement statistically. The hardware implementation of the proposed calibration requires single counter to construct the histogram, so that the extra area for the proposed calibration is smaller. Because the implementation is fully digital, it is easily implemented on digital LSIs such as FPGA, micro-processor, and SoC. Experiments with Xilinx Virtex-5 LX FPGA ML501 reveal that both the periods of the external clock and the ring oscillator are preferred as short as possible under more than twice of the range of measurement of TDC when the oscillation period of the ring oscillator is wider than that of the external clock for fast convergence. The required time for the proposed calibration is 0.08 ms, and the required hardware resources LUTs and FFs for the implementation on FPGA are 24.1% and 22.2% of the conventional implementation, respectively.

Successive approximation time-to-digital converter with vernier-level resolution

This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for multichannel timing built-out self-test (BOST) implementation on an FPGA chip. In order to reduce the number of buffers and DFFs in a conventional Flash TDC or Vernier TDC, successive approximation is applied to construct a SAR TDC when two timing inputs are repetitive (not shingle-shot). Besides, Vernier TDC has been added as the sub-circuit to form a two-step SAR+SAR-Vernier TDC architecture. LTspice and Xilinx ISE simulation have been performed to verify its feasibility. Also discussions on several TDC architectures as BOST are described.

Timing measurement BOST architecture with full digital circuit and self-calibration using characteristics variation positively for fine time resolution

This paper presents a time-to-digital converter (TDC) architecture to measure the timing difference between single-event two pulses with fine time resolution. Its features are as follows: (i) The architecture is based on stochastic process and statistics theory. (ii) It exploiting the stochastic variation in CMOS process for fine time resolution so that MOSFETs with minimum sizes are utilized. (iii) It needs a large number of D Flip-Flops (DFFs) for statistics but advanced fine CMOS technology can realize it. The larger the number of DFFs is, the finer the time resolution is. (iv) The self-calibration technique using the histogram method is applied to compensate the nonlinearity due to the circuit characteristics variation as well as timing skew by layout and routing. (v) The proposed TDC can be implemented with full digital circuit including the self-calibration circuit. Register-Transfer-Level (RTL) simulation has been conducted to validate the operation principle. RTL verification results indicate that the proposed stochastic architecture with self-calibration feature can realize a linear TDC with subpicosecond time resolution. The proposed TDC can be used for IC testing, high-speed data transfer testing and clock jitter measurement as well as physical experiments and laser ranging.