Daiki Hirabayashi

Multi-bit Sigma-Delta TDC Architecture with Improved Linearity

This paper describes the architecture and principles of operation of sigma-delta ( ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit ΣΔ TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity. Here we propose two methods to improve the overall TDC linearity: a data-weighted-average (DWA) algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our Matlab simulation results demonstrate the effectiveness of these approaches.

Phase noise measurement techniques using delta-sigma TDC

This paper describes two techniques for measuring phase noise of a clock using a delta-sigma time-to-digital converter (TDC). One technique uses a reference signal (which has only very small phase noise), and the other does not use a reference signal. Both proposed techniques can be implemented with relatively simple circuitry, due to the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be increased by using longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. Costly high-performance spectrum analyzers which average several-time phase measurement results over a long measurement time (about 10s order), are not needed for phase noise measurement with the proposed technique. The other technique, which differs in that it uses a self-referenced clock rather than a reference signal, has potential wide applications.

Timing measurement BOST with multi-bit delta-sigma TDC

This paper describes design and implementation of a multi-bit delta-sigma (ΔΣ) Time-to-Digital Converter (TDC) with Data-Weighted-Averaging (DWA) algorithm on analog FPGA. I/O interfacing circuits such as double-data-rate (DDR) memory interfaces are very important, and their low-cost, high-quality test is challenging. We propose here simple test circuitry for measuring digital signal timing of I/O interfacing circuits with high resolution and good accuracy. We focus on TDC applications of ΔΣmodulators (for fine-timing-resolution, digital output, and simple circuitry) and with multi-bit architecture (for short testing time). However, the multi-bit ΔΣ TDC suffers from delay mismatches among delay cells. Then we propose to apply the DWA algorithm for the delay cells in order to solve this problem. Our experimental results showed that the DWA algorithm improved the overall multi-bitΔΣ TDC linearity.

Experimental verification of timing measurement circuit with self-calibration

This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC using a Programmable System-on-Chip (PSoC), and measurement results show that TDC linearity is improved by the self-calibration. All TDC circuits, as well as the self-calibration circuits can be implemented as digital circuits, even by using FPGA instead of full custom ICs, so this is ideal for fine CMOS implementation with short design time.

A clock jitter reduction circuit using gated phase blending between self-delayed clock edges

A clock jitter reduction circuit is presented that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately fourfold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages.

A CMOS PWM Transceiver Using Self-Referenced Edge Detection

A CMOS pulsewidth modulation (PWM) transceiver circuit that exploits the self-referenced edge detection technique is presented. By comparing the rising edge that is self-delayed by about 0.5 T and the modulated falling edge in one carrier clock cycle, area-efficient and high-robustness (against timing fluctuations) edge detection enabling PWM communication is achieved without requiring elaborate phase-locked loops. Since the proposed self-referenced edge detection circuit has the capability of timing error measurement while changing the length of self-delay element, adaptive data-rate optimization and delay-line calibration are realized. The measured results with a 65-nm CMOS prototype demonstrate a 2-bit PWM communication, high data rate (3.2 Gb/s), and high reliability (BER> 10-12) with small area occupation (540 μm2). For reliability improvement, error check and correction associated with intercycle edge detection is introduced and its effectiveness is verified by 1-bit PWM measurement.

Multi-bit sigma-delta TDC architecture with self-calibration

This paper describes the architecture and principles of operation of sigma-delta (ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications; they offer good accuracy with short test times. In particular, we describe a multi-bit ΣΔ TDC architecture for fast testing. However, mismatches among delay cells in delay lines degrade the linearity there. Then we propose a self-calibration method that measures delay values using an improved ring oscillator circuit to improve the overall TDC linearity. Our MATLAB simulation results demonstrate the effectiveness of the proposed approach.

Multi-bit Sigma-Delta TDC Architecture for Digital Signal Timing Measurement

This paper describes the architecture (circuit design) and principles of operation of sigma-delta Sigma-Delta time-to-digital converters (TDC) for high-speed I/O interface circuit test applications, they offer good accuracy with short test times. In particular, we describe multi-bit ΣΔ TDC architectures for fast testing. However, mismatches among delay cells in delay lines degrade the linearity there. Then we propose two methods to improve the overall TDC linearity: a data-weighted averaging algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our MATLAB and Spectre simulation results demonstrate the effectiveness of these approaches.

Phase Noise Measurement and Testing with Delta-Sigma TDC

This paper describes a phase noise measurement and testing technique for a clock using a delta-sigma time-to-digital converter (TDC) and verifies its effectiveness with MATLAB simulations. The proposed technique can be implemented with relatively small circuitry, based on the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be finer with longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. High performance spectrum analyzers with long measurement time (several ten seconds order due to average of several-time phase measurement results), which are very costly in mass production testing, are not be needed for phase noise measurement with the proposed technique. Our simulation used the input clock of 1 MHz in several phase fluctuation cases, and we observed that the phase fluctuation spectrum at the expected frequency from TDC output power spectrum obtained by FFT. We also investigated the amount of phase fluctuation with our theoretical calculation, which agrees with the simulation results.

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges

Design of a clock jitter reduction circuit that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT is presented. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately four-fold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages.