Conor Rafferty

Iterative methods in semiconductor device simulation

This paper examines iterative methods for solving the semiconductor device equations. The emphasis is on fully coupled methods, because of the failure of decoupled methods for on-state devices. Using the PISCES-II device simulator as a vehicle, incomplete factorization and operator decomposition iterative methods are presented for solving the Newton equations. The dependencies of these methods on factors such as choice of variables, bias condition and initial guess are analyzed. The results are compared with sparse Gaussian elimination.

89-GHz f/sub T/ room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 AA, and a channel length of 0.15 mu m. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region.<<ETX>>

Device-level simulation of wave propagation along metal-insulator-semiconductor interconnects

A device-level simulation is presented for studying wave propagation along metal-insulator-semiconductor interconnects. A set of nonlinear equations is first formulated by combining the motion equations of charged carriers and Maxwells equations. The set of nonlinear equations is then transformed into the frequency domain, which leads to sets of nonlinear equations for the fundamental mode and its harmonics. Finally, the sets of nonlinear equations in the frequency domain are discretized using the finite-element method and solved using Newtons iterations. Special numerical enhancements are implemented to speed up the computational convergence and handle the boundary layer nature of the problem under study. This device-level simulation provides knowledge on field-carrier interactions, semiconductor substrate loss, and nonlinearity, as well as slow-wave and screening effects of charged carriers. This device-level simulation scheme enables a rigorous full-wave study of nonlinearity effects that arise from semiconductor substrates. Numerical examples for some practical material and geometrical parameters are included to illustrate capabilities and efficiency of the proposed device-level simulation scheme.

Velocity saturation effect on short-channel MOS transistor capacitance

To analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree quite well. Several causes of short-channel effects are explained by the simulations. Velocity saturation effects are found to play a key role in the gradual increase in Cgd. Also holes in the accumulation region and the two-dimensional effect or the influence of the back-gate field from the drain are important in explaining the short-channel effect of MOS transistor capacitance.

Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances

In order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree well. The causes of short-channel effects have been understood and explained by the simulations. Two-dimensional effects and velocity saturation are the main causes of short-channel effects in MOS transistor capacitances. Two-dimensional simulation was found to be a useful tool for studying mobility models, as well as for obtaining capacitance models for circuit simulation.

Computer-aids for analysis and scaling of extrinsic devices

Although intrinsic effects have been successfully modeled using computer analysis, the capability to characterize and predict extrinsic effects has lagged behind. Scaling of VLSI now requires coordinated analysis of all resistive, capacitive, and parasitic devices-especially those associated with isolation and CMOS well structures. This paper addresses the problem of intrinsic devices imbedded in a complete technology framework including parasitics. Results are presented for resistive and capacitive effects which influence intrinsic device performance. The role of velocity saturation on Cgdis explained. Analysis of isolation structures shows the importance of nonplanar analysis and effects of two-dimensional impurity distributions. An hierarchy of approaches for latch-up analysis is considered. Use, of circuit- like one-dimensional analysis can give good results for some holding conditions. However, transient two-dimensional (2D) results are needed to account for more complex triggering conditions. Results of 2D simulation show critical process-dependent effects of triggering. The PISCES program is demonstrated to be a powerful tool for analysis of both intrinsic and parasitic 2D device effects.

Novel Strain Relief Design for Multilayer Thin Film Stretchable Interconnects

Most electronic systems are rigid and inflexible. Many applications, however, require or benefit from conformable designs. To create efficient conformable systems, multilayer stretchable interconnects are necessary. A novel strain relief structure for multilayer stretchable interconnects is proposed. The numerical analysis shows that the proposed structure will function indefinitely when stretched as much as 20% of its initial length. Electromechanical measurements demonstrate that the onset of microcrack formation in the interconnects occurs, on average, after 89% elongation. These measurements also show that the structures are able to withstand elongations of up to 285%. Additionally, precise failure mechanisms, including interconnect straightening and microcrack formation are documented.

New n-well fabrication techniques based on 2D process simulation

For submicron device technology, 2D process modeling is essential. The need for shallow junctions and control of lateral dimensions of well and oxide isolation regions require well-characterized processes. This paper presents results obtained with SUPREM-IV which show fully numerical 2D coupled diffusion for both point defects and dopant atoms. Based on comparison of experimental results and parameter extraction for surface kinetic coefficients of point defects, SUPREM-IV is used to design a new n-well process with 37% reduction of the lateral well dimension. For dopant diffusion, the role of coupled point defects (interstitials and vacancies) and dopants are shown to give a unique result based on extracted surface recombination rates (1) and experimental data.

A conformal sensor for wireless sweat level monitoring

A conformal, wearable and wireless system for continuously monitoring the local body sweat loss during exercise is demonstrated in this work. The sensor system includes a sweat absorber, an inter-digitated capacitance sensor, and a communication hub for data processing and transmission. Experimental results show that the sensor has excellent sensitivity and consistent response to sweat rate and level. A 150% variation in the sensor capacitance is observed with 50μL/cm2 of sweat collected in the absorber. During wear tests, the sensor system is placed on the subjects right anterior thigh for measuring the local sweat response during exercise (eg. running), and the measured sweat loss (147μL) was verified by the weight change within the absorbent material (144mg). With a conformal and wireless design, this system is ideal for applications in sport performance, dehydration monitoring, and health assessment.

Design for reliability of multi-layer thin film stretchable interconnects

To date, nearly all electronic systems have been rigid and inflexible. However, there are many areas such as in biomedical devices in which these rigid electronics are less than ideal and which require new conformable electronic systems. In order to create effective, compact, and complex systems, stretchable interconnects must be designed to overlap one another in multiple layers. The circular strain relief structure described in this paper effectively redistributes the strain to the crest of the horseshoes of the interconnects themselves. Numerical analysis and simulations of the strain relief structures described in this paper indicate that the structures will function indefinitely when stretched up to a 20% elongation. In-situ electromechanical measurements show that the structures are able to withstand elongations of 285% or more before failing. Precise failure mechanisms including straightening of the interconnects and micro-crack formation are documented with images taken during the electromechanical tests.