Mark R. Pinto

Iterative methods in semiconductor device simulation

This paper examines iterative methods for solving the semiconductor device equations. The emphasis is on fully coupled methods, because of the failure of decoupled methods for on-state devices. Using the PISCES-II device simulator as a vehicle, incomplete factorization and operator decomposition iterative methods are presented for solving the Newton equations. The dependencies of these methods on factors such as choice of variables, bias condition and initial guess are analyzed. The results are compared with sparse Gaussian elimination.

A two-dimensional simulation of organic transistors

In this paper, we analyze the operation of organic thin-film transistors (TFTs) using two-dimensional (2-B) numerical simulation to: (1) validate the use of simple MOSFET theory to describe the above-threshold behavior; (2) clarify the subthreshold characteristics, and short-channel effects; and (3) illustrate the operation of organic bilayer devices. Our analysis clarifies a number of issues that can help in device design. We also point out differences between the material parameters used in Si-MOSFET and organic FET simulation, and discuss the circumstances under which a semiconductor device simulator can be used for the simulation of organic transistors.

A semi-empirical model of surface scattering for Monte Carlo simulation of silicon n-MOSFETs

A semi-empirical model of surface scattering for Monte Carlo simulation of electrons in the silicon inversion layer at 300 K is proposed. The model compares favorably with different sets of experimental electron effective mobility data over a wide range of normal electric fields, channel impurity concentrations, and substrate bias. Comparisons between Monte Carlo and drift-diffusion simulations show that the model is able to correctly predict the device termination currents in the regime where nonequilibrium transport effects are negligible. It is expected therefore that at small device lengths the Monte Carlo predictions are also quantitatively correct. >

Accurate trigger condition analysis for CMOS latchup

Two-dimensional device simulation is used to accurately predict both static and dynamic triggering conditions for CMOS latchup. Excellent agreement is obtained with experimental results for static trigger currents that cannot be modeled using lumped element approaches. For the first time, full transient two-dimensional simulation is performed to obtain a dynamic triggering threshold.

Verification of electron distributions in silicon by means of hot carrier luminescence measurements

This paper investigates the use of hot carrier luminescence (HCL) measurements as a mean for the verification of carrier energy distribution functions in submicron silicon devices subject to high electric fields. To this purpose, physically-based two-dimensional (2-D) simulations of the spectral distribution of HCL are compared with extensive experimental data on special purpose n/sup +//n/n/sup +/ test structures that demonstrate lateral field profiles similar to real MOSFETs without the obscuring effects of a gate electrode. Good agreement between measured and simulated data is observed over wide channel length, bias, and temperature ranges, thus providing for the first time a direct verification of simulated electron energy distributions in a MOSFET-like environment.

Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances

In order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree well. The causes of short-channel effects have been understood and explained by the simulations. Two-dimensional effects and velocity saturation are the main causes of short-channel effects in MOS transistor capacitances. Two-dimensional simulation was found to be a useful tool for studying mobility models, as well as for obtaining capacitance models for circuit simulation.

Computer-aids for analysis and scaling of extrinsic devices

Although intrinsic effects have been successfully modeled using computer analysis, the capability to characterize and predict extrinsic effects has lagged behind. Scaling of VLSI now requires coordinated analysis of all resistive, capacitive, and parasitic devices-especially those associated with isolation and CMOS well structures. This paper addresses the problem of intrinsic devices imbedded in a complete technology framework including parasitics. Results are presented for resistive and capacitive effects which influence intrinsic device performance. The role of velocity saturation on Cgdis explained. Analysis of isolation structures shows the importance of nonplanar analysis and effects of two-dimensional impurity distributions. An hierarchy of approaches for latch-up analysis is considered. Use, of circuit- like one-dimensional analysis can give good results for some holding conditions. However, transient two-dimensional (2D) results are needed to account for more complex triggering conditions. Results of 2D simulation show critical process-dependent effects of triggering. The PISCES program is demonstrated to be a powerful tool for analysis of both intrinsic and parasitic 2D device effects.

An efficient numerical model of CMOS latch-up

A one-dimensional numerical model of latch-up in bulk CMOS structures is presented. The model simulates the triggering and sustaining regimes of the parasitic SCR, yielding results nearly equivalent to those obtained using two-dimensional analysis, but with two orders of magnitude-lower computational cost. The model is used to obtain the SCR switching characteristics of typical CMOS based on two-dimensional impurity cross sections, and parameter sensitivities are examined.