Cooper S. Levy

A wideband voltage mode Doherty power amplifier

This paper presents a new wideband Doherty Amplifier technique that can achieve high efficiency while maintaining excellent linearity. By modifying a “forgotten” topology originally proposed by Doherty, a new Doherty Amplifier architecture is realized with two voltage mode PAs and transformers, thus eliminating a narrowband impedance inverter. The voltage mode PA is implemented with a switched capacitor PA known for its excellent linearity. The PA is fabricated in 65 nm low-leakage CMOS and achieves 24 dBm saturated power (at standard supply voltage) with 45%/34% PAE at peak and 5.6dB back-off over 750 MHz to 1050 MHz 1dB bandwidth. With memory-less linearization, this PA can transmit 40 MHz 256-QAM 9dB PAPR 802.11ac modulation centered at 900 MHz meeting the spectral mask with measured EVM of -34.8dB and 22% PAE without backing-off or equalization.

Supply-Scaling for Efficiency Enhancement in Distributed Power Amplifiers

Distributed amplifiers (DAs) feature large bandwidth but relatively low gain and power efficiency. This paper presents a supply-scaling technique to improve the efficiency of a mm-wave DA while maintaining a broadband

A 105-GHz, supply-scaled distributed amplifier in 90-nm SiGe BiCMOS

50\Omega

2.8 A Class-G voltage-mode Doherty power amplifier

match. An analysis of interstage load modulation and the effects of shunt dc-feed inductors on distributed operation is provided. A single-ended, eight-stage DA is designed in a 90 nm SiGe BiCMOS process. The fabricated amplifier has a gain of 12 dB over a 3 dB bandwidth from 14-105 GHz. The measured peak output power is 17 dBm with a peak power-added efficiency (PAE) of 12.6% at 50 GHz and 3 dB power bandwidth greater than 70 GHz. The DA occupies an area of 2.65 mm × 0.57 mm, and total dc power consumed from four scaling voltage supplies is 297 mW.

Voltage Mode Doherty Power Amplifier

Distributed amplifiers (DAs) feature large bandwidth but relatively low gain and power efficiency. We present a supply-scaling technique to enhance the efficiency of a broadband DA. The presented eight-stage amplifier has a gain of 12 dB over a 3 dB bandwidth from 14-105 GHz and achieves peak output power of 17 dBm at 12.6% power-added efficiency (PAE) at 50 GHz. The DA is designed in a 90-nm SiGe BiCMOS process and occupies an area of 2.65 mm × 0.57 mm. Total dc power consumed is 297 mW.

A 14-GHz, 22-dBm Series Doherty Power Amplifier in 45-nm CMOS SOI

In modern communication, wideband and high-spectral-efficiency modulation results in high peak-to-average power ratio (PAPR), up to 8 to 10dB. Well-known PA-efficiency-enhancement techniques, such as Doherty and outphasing, offer reduced efficiency improvement beyond 6dB back-off, limiting the efficiency enhancement obtainable with high PAPR modulation. Recent works have shown that a combination of different techniques [1–3] can result in improved efficiency well beyond 6dB back-off. However, these combined techniques have come at a cost of glitches due to mode-transitions, when power supply voltage or load impedance undergo large variations at critical power levels. In [1,2] switching between power supply voltages causes significant glitches, which degrade the EVM and ACPR of the transmitted signal. In [1], reasonable EVM is achieved, by reducing the average output power so that power supply switching is less frequent. A “skipping window” technique is proposed in [3] to skip high-frequency mode-transitions reducing overall glitching. While this improves the ACPR, the efficiency is degraded since there is no enhancement during a skipped transition.

A 6-41 GHz Distributed Amplifier with Supply Scaling for Efficiency Enhancement

This paper presents a new wideband Doherty amplifier technique that can achieve high efficiency while maintaining excellent linearity. By modifying a “forgotten” topology originally proposed by Doherty, a new Doherty amplifier architecture is realized with two voltage mode power amplifiers (PAs) and transformers, thus eliminating a narrowband impedance inverter. The voltage mode PA is implemented using switched capacitor PA techniques. The PA is fabricated in 65-nm low-leakage CMOS and achieves 24-dBm saturated power (at the standard supply voltage) with PAE of 45% at peak power and 34% at 5.6-dB back-off over 750 to 1050 MHz 1 dB bandwidth. With memory-less linearization, the PA can transmit 40 MHz 256-QAM 9 dB peak-to-average power ratio 802.11ac modulation centered at 900 MHz meeting the spectral mask with measured EVM of −34.8 dB and 22% PAE without backing off or equalization.

A CMOS SOI Stacked Shunt Switch with Sub-500ps Time Constant and 19-Vpp Breakdown

This paper presents a new series Doherty power amplifier (SDPA) with a single-ended output that eliminates transformers in the output matching network. The series power combining architecture offers higher output power in scaled CMOS compared to conventional Doherty PAs and is amenable to integration at microwave and millimeter wave bands. The SDPA is implemented in 45-nm CMOS SOI and achieves a peak output power of 22-dBm and PAE of 24% and 20% at peak and 6 dB back-off powers, respectively.

Improved Performance of Zinc Oxide Thin Film Transistor Pressure Sensors and a Demonstration of a Commercial Chip Compatibility with the New Force Sensing Technology

This work explores wideband efficiency enhancement techniques for distributed amplifiers. The concept of a supply-scaled distributed amplifier (SSDA) utilizing a band-pass distributed amplifier with multiple supply voltages is discussed. A prototype amplifier is fabricated in a 0.15μm GaN on a 2mil SiC process. The chip is measured and shows a significant improvement in drain efficiency and power added efficiency with supply scaling.

A 30.9 dBm, 300 MHz 45-nm SOI CMOS Power Modulator for Spread-Spectrum Signal Processing at the Antenna

This work demonstrates a shunt stacked-FET switch with both high switching speed (~1ns) and high RF voltage handling capability (30 dBm). A key development in the implementation of this stacked structure is a dynamic gate bias adjustment to track the voltage swing. Measured performance for a shunt capacitor-switch network fabricated in 45-nm CMOS SOI (Leff = 40 nm) is characterized. The switch achieves a RonCoff time constant of less than 500ps, and is shown to handle a 19Vpp RF signal swing. These characteristics enable use in digital dynamic load modulation of power amplifiers at bandwidths above 10 MHz.