Sreedhar Natarajan

Impact of negative bias temperature instability on digital circuit reliability

We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Further, we show that the static noise margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases.

A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process

A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process

A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic process. Address access time for the memory is less than 30 ns while consuming 0.57 mW/MHz at 1.37 V. An eFRAM density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

PD-SOI and FD-SOI: a comparison of circuit performance

Over the past few years SOI has received much attention as an integrated circuit substrate that may confer advantages in performance over conventional bulk silicon IC processing. Partially and Fully Depleted SOI have been evaluated as possible successors to bulk silicon substrates for high performance circuits. Device characteristics and circuit design on these two forms of SOI are compared and contrasted.

Technological innovations to advance scalability and interconnects in bulk and SOI

With technology scaling rapidly, there is increased need for improved performance. While improved performance can be achieved with lower threshold voltages, leakage will be a major issue at technologies below 0.1/spl mu/m/sub ./ Interconnect scaling is not expected to keep up with component scaling, resulting in higher capacitance losses and challenges in signal routing. We consider how scaling will impact design for low power and high performance applications. SOI may be a solution for some issues like SER due to the presence of buried oxide. Performance can be enhanced by SOI technology due to the absence of junction capacitance. The combination of short gate length technologies and PD-SOI can mitigate performance degradation due to interconnect capacitances and leakage.

SOI SRAM design advances & considerations

SOI is a relatively new introduction in memory design and its use can improve performance. Bit-line capacitance and pass gate loads are major sources of current discharge in SOI SRAM cells. Currents from bit line capacitance and cell leakage can corrupt the cell data. SOI improves the soft error rate due to Alpha particles, mainly because of the presence of buried oxide. This paper is a brief tutorial on SOI SRAM design issues, leakages and soft error rates.

Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference

The 30 papers in this special issue were among those presented at the IEEE International Solid-State Circuits Conference (ISSCC), held in San Francisco, CA, February 11-15, 2007. There are four areas: Digital Papers; Memory Papers; Signal Processing Papers; and Technology Direction Papers.