Resve A. Saleh

Performance evaluation and design trade-offs for network-on-chip interconnect architectures

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

System-on-Chip: Reuse and Integration

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

Clock skew verification in the presence of IR-drop in the power distribution network

Clocks are perhaps the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of clock signals directly impact the performance of a very large scale integrated chip. Clock skew verification requires high accuracy and is typically performed using circuit simulators. However in high-performance deep-submicrometer digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher current load on the power distribution network with the potential for substantial power grid voltage (IR)-drop. This IR-drop affects the clock timing and must be taken into account in the verification process. Since IR-drop is a full-chip phenomenon, the use of standard circuit simulation on both the clock circuitry and the power-grid is not practical. In this paper, we present a new methodology for the verification of clock delay and skew. An iterative technique is presented for clock simulation in the presence of full-chip dynamic IR-drop. The effect of IR-drop on the timing of clock signals is quantified on a small example, and demonstrated on a large chip.

Simulation and analysis of transient faults in digital circuits

To study the effect of transient faults in large digital circuits, a simulation tool called DYNAMO has been developed. It allows transient faults to be introduced in a circuit during a transient analysis so that its behavior can be observed and recorded. For efficiency, a dynamic mixed-mode simulation approach is employed whereby the representation of various portions of the circuit may switch between different levels of abstraction during the simulation, as dictated by the location of the transient fault and the resulting behavior of the circuit. Experiments have shown very encouraging results with significant speedups in CPU run times relative to the previous approach. The results of transient-fault simulation using the DYNAMO program on an avionic control microprocessor are also included. >

Incremental techniques for the identification of statically sensitizable critical paths

This paper describes new algorithms for finding the K-most critical paths, checking static sensitizability of these paths, and performing incremental timing verification on combinational circuits. The static sensitization method uses binary decision diagrams to avoid costly backtracking operation used in other path analysis programs. The speed and efficiency of the techniques are demonstrated individually using the ISCAS benchmark circuits, and then together in a timing optimization loop.

Programmable logic IP cores in SoC design: opportunities and challenges

As SoC design enters into mainstream usage, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. These cores are like any other IP in the SoC design methodology, except that their function can be changed after fabrication. This paper outlines ways in which programmable logic cores can simplify SoC design, and describes some of the challenges that must be overcome if the use of programmable logic cores is to become a mainstream design technique.

Parallel circuit simulation on supercomputers

Circuit simulation is a very time-consuming and numerically intensive application, especially when the problem size is large as in the case of VLSI circuits. To improve the performance of circuit simulators without sacrificing accuracy, a variety of parallel processing algorithms have been investigated. Research in the field of parallel circuit simulation is surveyed, and the ongoing research in this area at the University of Illinois is described. Both standard and relaxation-based approaches are considered. In particular, the forms of parallelism available within the direct method approach, used in programs such as SPICE2 and SLATE, and within the relaxation-based approaches, such as waveform relaxation, iterated timing analysis, and waveform-relaxation-Newton, are described. The specific implementation issues addressed are primarily related to general-purpose multiprocessors with a shared-memory architecture having a limited number of processors, although many of the comments apply to a number of other architectures. >

Testing Network-on-Chip Communication Fabrics

Network-on-chip (NoC) communication fabrics will be increasingly used in many large multicore system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test budget. In this paper, we present a novel methodology for testing such NoC architectures. The proposed methodology offers a tradeoff between test time and on-chip self-test resources. The fault models used are specific to deep submicrometer technologies and account for crosstalk effects due to interwire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to the components under test in a recursive manner. It exploits the inherent parallelism of the data transport mechanism to reduce the test time and, implicitly, the test cost. We also describe a suitable test-scheduling approach. In this manner, the test methodology developed in this paper is able to reduce the test time significantly as compared to previously proposed solutions, offering speedup factors ranging from 2x to 34x for the NoCs considered for experimental evaluation.

The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation

The speedups derived from the exploitation of the waveform properties are discussed and simple procedures are provided to compute empirical upper bounds on the speed improvement when these properties are exploited. These upper bounds are used to explain the reasons for the variations in the speedups and to evaluate the performance of two circuit simulation algorithms based on nonlinear relaxation that are implemented in the SPLICE3 program. The first algorithm is an advanced version of the iterated timing analysis (ITA) algorithm that exploits the latency property. The second algorithm is a new event-driven multirate integration scheme, based on ITA, that exploits multirate behavior of circuits. It also uses a novel event-driven approach to handle step rejections called selective-backup. >

Exact evaluation of diagnostic test resolution

The authors introduce a new measure of the diagnostic resolution of a test set: the sizes of all equivalence classes in the circuit under the test set. This measure is a better indicator of the diagnostic capabilities of a test set than single-value metrics based on undistinguished pairs of faults or completely distinguished faults. A symbolic algorithm for computing equivalence class sizes has been used to evaluate the diagnostic resolution of deterministic single-stuck-at fault test sets for ISCAS combinational and sequential benchmark circuits.<<ETX>>