Cristiano Forzan

Statistical static timing analysis: A survey

As the device and interconnect physical dimensions decrease steadily in modern nanometer silicon technologies, the ability to control the process and environmental variations is becoming more and more difficult. As a consequence, variability is a dominant factor in the design of complex system-on-chip (SoC) circuits. A solution to the problem of accurately evaluating the design performance with variability is statistical static timing analysis (SSTA). Starting from the probability distributions of the process parameters, SSTA allows to accurately estimating the probability distribution of the circuit performance in a single timing analysis run. An excellent survey on SSTA was recently published [D. Blaauw, K. Chopra, A. Srivastava, L. Scheffer, Statistical timing analysis: from basic principles to state of the art, IEEE Trans. Computer-Aided Design 27 (2008) 589-607], where the authors presented a general overview of the subject and provided a comprehensive list of references. The purpose of this survey is complementary with respect to Blaauw et al. (2008), and presents the reader a detailed description of the main sources of process variation, as well as a more in-depth review and analysis of the most important algorithms and techniques proposed in the literature that have been applied for an accurate and efficient statistical timing analysis.

Why we need statistical static timing analysis

As technology continues to advance deeper into the nanometer regime, a tight control on the process parameters is increasingly difficult. As a consequence, variability has turned out to be a dominant factor in the design of complex ICs. Traditional static timing analysis (STA) is becoming insufficient to accurately evaluate the process variation impact on the design performance considering the increasing number of process, power supply voltage, and temperature (PVT) corners. In contrast, statistical static timing analysis (SSTA) is a promising innovative technique to handle increasingly larger environmental and process fluctuations, especially on-chip parameter variations. However, the statistical approach needs a set of costly additional data such as an accurate process variation description, and a statistical standard cell library characterization. In this paper, STA and SSTA are applied on a real industrial design to compare the two techniques, in terms of both accuracy and cost. From our analysis, we have concluded that the potential advantages offered by SSTA exceed the additional library characterization cost and process data assembly effort.

EMC-aware design on a microcontroller for automotive applications

In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip power rail noise is one of the most detrimental sources of electromagnetic (EM) conducted emissions, since it propagates to the board through the power and ground I/O pads. In this work we investigate the impact of power rail noise on EMI, and we show that by limiting this noise source it is possible to drastically reduce the conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and board designers to asses the power integrity and predict the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.

Accurate and efficient macromodel of submicron digital standard cells

In this paper a new analytic gate delay modelingtechnique is presented that allows to accuratelyreproduce the timing behavior of deep submicron digitalstandard cells for a large range of operating conditions.The proposed technique sensibly improves the accuracyof the existing analytic delay models and it usuallyrequires less simulations for the cell characterization.Moreover it is compatible with the most advanced interconnectdelay models that have been recently proposed inthe literature.

Design methodologies and architecture solutions for high-performance interconnects

In deep sub-micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex system-on-chip (SoC) designs. For technologies of 0.25 /spl mu/m and below, wiring capacitance dominates gate capacitance, thus rapidly increasing the interconnect-induced delay. Moreover, the coupling capacitance becomes a significant portion of the on-chip total wiring capacitance, and coupling between adjacent wires cannot be considered as a second-order effect any longer. As a consequence, the traditional top-down design methodology is ineffective, since the actual wiring delays can be computed only after layout parasitic extraction, when the physical design is completed. Fixing all the timing violations often requires several time-consuming iterations of logical and physical design, and it is essentially a trial-and-error approach. Increasingly tighter time-to-market requirements dictate that interconnect parasitics must be taken into account during all phases of the design flow, at different level of abstractions. However, given the aggressive technology scaling trends and the growing design complexity, this approach is only temporarily ameliorate the interconnect problem. We believe that in order to achieve gigascale designs in the nanometer regime, a novel design paradigm, based on new forms of regularity and newly created IP (intellectual property) blocks must be developed, to provide a direct path from system-level architectural exploration to physical implementation.

A complete methodology for an accurate static noise analysis

In signal integrity analysis, the joint effect of propagated noise through library cells, and of the noise injected on a quiet net by neighboring switching nets through coupling capacitances, must be considered in order to accurately estimate the overall noise impact on design functionality and performances.In this work a general macromodel that considers the impact of the cell non-linearity on the noise glitch waveform is proposed, and a new approach that allows to accurately and efficiently modeling the cell non-linear effects in Static Noise Analysis is presented. Experimental results confirm that existing noise analysis approaches based on linear superposition of the propagated and crosstalk-injected noise can be highly inaccurate, thus impairing the sign-off functional verification phase, and demonstrate the effectiveness of our method that can be seamlessly integrated into noise analysis tools.

Power supply selective mapping for accurate timing analysis

In Deep Sub-Micron technologies post-layout timing analysis has become the most critical phase in the verification of large System-on-Chip (SoC) designs with several power-hungry blocks. The impact of coupling capacitances has been adequately analyzed, and modern signal integrity analysis tools can effectively consider the crosstalk-induced delay. However, an increasingly important factor that can introduce a severe performance loss is the power supply noise. As technology advances into the nanometer regime, the operating frequencies increase, and clock gating has emerged as an effective technique to limit the power consumption in block-based designs. As a consequence, the amplitude of the supply voltage fluctuations has reached values where techniques to include the effect of power supply noise into timing analysis based on linear models are no longer adequate, and the non-linear dependence of cell delay from supply voltage must be considered. In this work we present a practical methodology that accurately takes into account the power supply noise effects in static timing analysis, which can be seamlessly included into an industrial sign-off design flow. The experimental results obtained from the timing verification of an industrial SoC design have demonstrated the effectiveness of our approach.

Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis

In signal integrity analysis, the joint effect of propagated noise through library cells, and of the noise injected on a quiet net by neighboring switching nets through coupling capacitances, must be considered in order to accurately estimate the overall noise impact on design functionality and performances. In this work the impact of the cell non-linearity on the noise glitch waveform is analyzed in detail, and a new macromodel that allows to accurately and efficiently model the non-linear effects of the victim driver in noise analysis is presented. Experimental results demonstrate the effectiveness of our method, and confirm that existing noise analysis approaches based on linear superposition of the propagated and crosstalk-injected noise can be highly inaccurate, thus impairing the sign-off functional verification phase.