Davide Pandini

Congestion-Aware Logic Synthesis

In this era of Deep Sub-Micron (DSM) technologies, the impact of interconnects is becoming increasingly important as it relates to integrated circuit (IC) functionality and performance. In the traditional top-down IC design flow, interconnect effects are first taken into account during logic synthesis by way of wireload models. However, for technologies of 0.25 /spl mu/m and below, the wiring capacitance dominates the gate capacitance and the delay estimation based on fanout and design legacy statistics can be highly inaccurate. In addition, logic block size is no longer dictated solely by total cell area, and is often limited by wiring area resources. For these reasons, wiring congestion is an extremely important design factor, and should be taken into consideration at the earliest possible stages of the design flow. In this paper we propose a novel methodology to incorporate congestion minimization within logic synthesis, and present results for industrial circuits that validate our approach.

Understanding and addressing the impact of wiring congestion during technology mapping

Traditionally, interconnect effects are taken into account duringlogic synthesis via wireload models, but their ineffectiveness forDSM technologies has been demonstrated and various physicalsynthesis approaches have been spawned to address the problem. Ofparticular interest is that logic block size is no longer dictatedexclusively by total cell area, yet synthesis optimizationobjectives are aimed specifically at minimizing the number and sizeof cells. Methodologies that incorporate congestion within thelogic synthesis objective function have been proposed in[9][10][11] and [15]; however, as we will demonstrate, predictingthe true congestion prior to layout is not possible, and theefficacy of any approach can only be evaluated after routing iscompleted within the fixed die size. In this paper we propose apractical, complete methodology which first performscongestion-aware technology mapping using a global weighting factorfor the cost function [15], and then applies incremental localizedunmapping and remapping on congested areas. This complete approachaddresses the problem that one global factor is not ideally suitedfor all regions of the designs. Most importantly, through theapplication of this methodology to industrial examples we will showthat any attempt at a purely top-down single-pass congestion-awaretechnology mapping is merely wishful thinking.

Statistical static timing analysis: A survey

As the device and interconnect physical dimensions decrease steadily in modern nanometer silicon technologies, the ability to control the process and environmental variations is becoming more and more difficult. As a consequence, variability is a dominant factor in the design of complex system-on-chip (SoC) circuits. A solution to the problem of accurately evaluating the design performance with variability is statistical static timing analysis (SSTA). Starting from the probability distributions of the process parameters, SSTA allows to accurately estimating the probability distribution of the circuit performance in a single timing analysis run. An excellent survey on SSTA was recently published [D. Blaauw, K. Chopra, A. Srivastava, L. Scheffer, Statistical timing analysis: from basic principles to state of the art, IEEE Trans. Computer-Aided Design 27 (2008) 589-607], where the authors presented a general overview of the subject and provided a comprehensive list of references. The purpose of this survey is complementary with respect to Blaauw et al. (2008), and presents the reader a detailed description of the main sources of process variation, as well as a more in-depth review and analysis of the most important algorithms and techniques proposed in the literature that have been applied for an accurate and efficient statistical timing analysis.

A fully-automated desynchronization flow for synchronous circuits

Variability is one of the fundamental problems faced by nano-scale electronic circuits and is expected to become even worse as process technology scales. Desynchronization is a design methodology, which converts a synchronous gate- level circuit into a more robust asynchronous one. In this paper, we describe the first fully-automated desynchronization design flow, based only on contemporary synchronous EDA tools and a new point tool for performing the desynchronization transformation. The flow was used to implement, down to mask layout level, a simple pipelined processor in a 90 nm industrial library. We show that the desynchronization methodology can be easily integrated into contemporary industrial EDA flows. Results, on the design implemented, indicate that desynchronized circuits exhibit increased variability tolerance and better average case performance, for a small area and power overhead.

An ultra-low energy asynchronous processor for wireless sensor networks

This paper describes the design flow used for an asynchronous 8-bit processor implementing the Atmel AVR instruction set architecture. The goal is to show dramatic reductions in power and energy with respect to the synchronous case, while retaining essentially a traditional design flow. The processor was implemented in a 130nm technology using desynchronization, starting from an initial design downloaded from OpenCores.org. It consumes 14 pJ per instruction to deliver 170 MIPS at 1.2 V, and 2.7 pJ per instruction to deliver 48 MIPS at 0.54 V. It thus dramatically improves the energy consumed per instruction with respect to previous results from the literature

Why we need statistical static timing analysis

As technology continues to advance deeper into the nanometer regime, a tight control on the process parameters is increasingly difficult. As a consequence, variability has turned out to be a dominant factor in the design of complex ICs. Traditional static timing analysis (STA) is becoming insufficient to accurately evaluate the process variation impact on the design performance considering the increasing number of process, power supply voltage, and temperature (PVT) corners. In contrast, statistical static timing analysis (SSTA) is a promising innovative technique to handle increasingly larger environmental and process fluctuations, especially on-chip parameter variations. However, the statistical approach needs a set of costly additional data such as an accurate process variation description, and a statistical standard cell library characterization. In this paper, STA and SSTA are applied on a real industrial design to compare the two techniques, in terms of both accuracy and cost. From our analysis, we have concluded that the potential advantages offered by SSTA exceed the additional library characterization cost and process data assembly effort.

Clock distribution techniques for Low-EMI design

In modern digital ICs, the increasing demand for performance and throughput requires higher operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip clock signals with fast rise/fall times are among the most detrimental sources of electromagnetic (EM) noise, since not only they generate radiated emissions, but they also have a large impact con the conducted emissions, as the power rail noise localized in close proximity of the toggling clock edges propagates to the board through the power and ground pins. In this work, we analyze the impact of different clock distribution solutions on the spectral content of typical onchip waveforms, in order to develop an effective methodology for EMC-aware clock-tree synthesis, which globally reduces the EM emissions. Our approach can be seamlessly integrated into a typical design flow, and its effectiveness is demonstrated with experimental results obtained from the clock distribution network of an industrial digital design.

Global and local congestion optimization in technology mapping

In this era of deep submicrometer technologies, interconnects are becoming increasingly important as their effects strongly impact the integrated circuit (IC) functionality and performance. Moreover, logic block size is no longer determined exclusively by total cell area and is often limited by wiring area. However, synthesis optimization objectives are focused on minimizing the number and size of library cells. Methodologies that incorporate congestion within the logic synthesis objective function have been proposed in the past. Nevertheless, we will demonstrate that predicting the true congestion prior to layout is not possible, and the effectiveness of any congestion minimization approach can only be evaluated after routing is completed within the fixed die size. In this paper, we propose a practical, complete methodology which first performs congestion-aware technology mapping using a global weighting factor for the technology-dependent synthesis cost function and then applies incremental localized unmapping and remapping on layout congested areas. This complete approach addresses the problem that one global factor is not suited for all layout regions of the design, which might have very different routing demands. Most importantly, through the application of this methodology to industrial examples, we will show that any attempt at a purely top-down single-pass congestion-aware technology mapping is merely wishful thinking.

EMC-aware design on a microcontroller for automotive applications

In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip power rail noise is one of the most detrimental sources of electromagnetic (EM) conducted emissions, since it propagates to the board through the power and ground I/O pads. In this work we investigate the impact of power rail noise on EMI, and we show that by limiting this noise source it is possible to drastically reduce the conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and board designers to asses the power integrity and predict the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.

A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis

Performance, power, and functionality, yield and manufacturability are rapidly becoming additional critical factors that must be considered at higher levels of abstraction. A possible solution to improve yield and manufacturability is based on the detection of regularity at logic level This paper focuses its attention on regularity extraction, after technology independent logic synthesis, to detect recurring functionalities during logic synthesis and thus constraining the physical design phase to exploit the regular netlist produced. A fast heuristic to the template identification is proposed and analyzed on a standard set of benchmarks both sequential and combinational.