Curtis Walter Preuss

A 2 GB/s high speed link with differential simultaneous bi-directional IO

The data bandwidth of an existing 1 GB/s high speed link is increased to 2 GB/s by use of differential simultaneous bi-directional signaling. This signaling technique allows a physical channel to carry two independent data streams, effectively doubling the data rate per IO. The driver also provides digital precompensation to counteract intersymbol interference due to skin effect attenuation.

A 1GB/S SCI link in 0.8/spl mu/m BiCMOS

It has become increasingly evident that the performance demands of modern microprocessors are rapidly outstripping the capability of traditional multidrop busses to support the necessary data bandwidth, especially in symmetric multi-processor (SMP) configurations. The definition of a replacement for the traditional bus with a packetized network based on unidirectional point-to-point links was undertaken under the auspices of the IEEE Microprocessor Standards Committee, resulting in the IEEE 1596-1992 Scalable Coherent Interface Standard (SCI). This chip is a prototype fabricated to evaluate the feasibility of implementing a full-speed SCI link in standard 0.8/spl mu/m BiCMOS.