Frank D. Ferraiolo

High-speed source-synchronous interface for the IBM System z9 processor

As mainframes evolve and deliver higher performance, technologists are focusing less on processor speed and more on overall system performance to create optimized systems. One important area of focus for performance improvement involves chip-to-chip interconnects, with their associated bandwidths and latencies. IBM and related computer manufacturers are optimizing the characteristics of interconnects between processors as well as between processors and their supporting chip sets (local cache, memory, I/O bridge). This paper describes the IBM proprietary high-speed interface known as Elastic Interface (EI), which is used for nearly all chip-to-chip communication in the IBM System z9TM. In particular, EI is a generic high-speed, source-synchronous interface used to transfer addresses, controls, and data between CPUs, L2 caches, memory subsystems, switches, and I/O hubs. The EI has single-ended data lines, resulting in twice the performance (bandwidth per pin) of similar buses operating with two differential lines per signal.

IBM Enterprise Systems multimode fiber optic technology

This paper describes the first implementation of optical fiber technology for the I/O channel connections of the IBM Enterprise Systems Connection (ESCON™) Architecture™. The ESCON optical link line rate is 200 megabits per second and is capable of transmission over distances of 3 km. The link is composed of a serializer, electro-optic transmitter, duplex fiber optic cable, electro-optic receiver, and deserializer. The serializer and deserializer respectively perform the conversions from parallel to serial and serial to parallel formats. The clock which is used to retime the serial data in the deserializer is extracted from the encoded serial signal using a phase-locked loop (PLL) technique. The optical link technology selected to achieve the data processing system requirements is InGaAsP/InP 1300-nm LED, InGaAsP/InP PIN photodiode, and multimode optical fiber. A duplex fiber jumper cable is designed with a rugged, low-profile, polarized connector, with a unique protective cap which recedes as it is mated. The optical link loss budget is determined by dividing the link into two major categories: available optical power and cable plant loss. The link design ensures that the minimum available power is greater than the maximum cable plant loss. The design parameters and trade-offs of the optical link are discussed in this paper. Unique measurement techniques and tools to ensure reliable and consistent link performance are described.

A clock methodology for high-performance microprocessors

This paper discusses an effective clock methodology for the design of high-performance microprocessors. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to minimize skew, hierarchical clock wiring, automated verification, an interface to the Cadence Design Framework II™ environment, and a complete network model of the clock distribution, including loads. This clock methodology enabled creation of the entire clock network, including verification, in less than three days with approximately 180 ps of skew.

A Clock Methodology for High-Performance Microprocessors

This paper discusses an effective clock methodology for the design of high-performance microprocessors. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to minimize skew, hierarchical clock wiring, automated verification, an interface to the Cadence Design Framework II™ environment, and a complete network model of the clock distribution, including loads. This clock methodology enabled creation of the entire clock network, including verification, in less than three days with approximately 180 ps of skew.

IBM Power5 bus designs for on- and off-module connections

This work overviews the interface choices made for the 1:1 on-module buses and the 2:1 off-module buses. Custom circuits used, data recovery methods, signal integrity design and the system verification using register based diagnostics and eye margin mapping. The hardware based verification methods that heavily rely on the interface register based diagnostics and margin mapping are explained.

A 5.4mW 0.0035mm 2 0.48ps rms -jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS

A CDR circuit for serial link receivers usually requires a multi-phase generator and a number of phase rotators to produce data and edge clocks. The most commonly used architecture is a dual-loop CDR where a DLL (or PLL) generates k equidistantly spaced clock phases that are fed into n/2 phase rotators, where n is the number of sampling latches in the CDR [1]. Another method was proposed in [2], where the multi-phase generation and phase shifting is achieved at the same time in a single PLL, in this case achieving phase-adjustment capability through the weighted summing of charge-pump outputs for several phases. This approach eliminates the additional delay associated with using phase rotators and simplifies the overall design. However, all these conventional methods require either a PLL or a DLL, blocks that demand the largest share of power consumption and of silicon area in the CDR circuit.