D. De Caro

Booth folding encoding for high performance squarer circuits

Combined Booth encoding and folding techniques are proposed to design squarer circuits using either carry-save or Wallace tree addition techniques. The Booth-folded technique is compared with previous state of the art squarer architectures, showing that a remarkable improvement in timing, power and area performances can be gained both for carry-save and Wallace tree cases. Experimental results, that use built-in-self-test for measuring on chip squarer performance, are presented. The measurements confirm the advantages of the Booth-folded architecture.

Direct digital frequency synthesizers using high-order polynomial approximation

Two 80 MHz 0.35 /spl mu/m 3.3V CMOS ROM-less DDFS using polynomial approximation are compared with Cordic-based circuits. A 60 dBc SFDR DDFS uses 2nd-order polynomials and 0.18 mm/sup 2/, with 15 mW dissipation. An 80 dBc SFDR DDFS uses 3rd-order polynomials and 0.44 mm/sup 2/, with 35 mW dissipation.

Low-power flip-flops with reliable clock gating

Abstract The paper presents two gated flip-flops aimed at low-power applications. The proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. The presented circuits overcome the clock duty-cycle limitation of previously reported gated flip-flops. Circuit simulations with the inclusion of parasitics show that sensible power dissipation reduction is possible if the input signal has reduced switching activity. A 16-bit counter and an audio sampler register are presented as examples of low-power applications.

ROM-less direct digital frequency synthesizers exploiting polynomial approximation

A new approach to design a ROM-less direct digital frequency synthesizer (DDFS) is presented. An optimized polynomial interpolation technique has been used to achieve a 60 dBc or 80 dBc spurious-free dynamic range. Also, in the paper a new technique for designing efficient circuits for the evaluation of polynomial functions is presented. The new DDFS compares favorably with state of the art DDFSs designed using the CORDIC algorithm.

Direct digital frequency synthesis with dual-slope approach

A new technique for phase to sine mapping in direct digital frequency synthesizers (DDFSs) is presented. With respect to previously proposed piecewise linear Taylor and Chebyshev approaches, novel technique reduces either ROM size or arithmetic hardware complexity, without decreasing accuracy. Simulation results for a 0.35/spl mu/m technology show a substantial increase in performances with respect to Taylor and Chebyshev DDFSs.

A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25/spl mu/m CMOS

Multipartite table methods are used in the implementation of a direct digital frequency synthesizer. Two quadrature 13b outputs are produced with a SFDR >90dB and a frequency resolution of 0.15Hz at a 630MHz clock frequency. The 0.25mum CMOS chip occupies 0.063mm2 and dissipates 76mW from a 2.5V supply at 630MHz

Shuffled serial adder: an area-latency effective serial adder

The shuffled adder, a novel serial adder with a latency proportional to log/sub 2/N, where N is the operand width, is presented. It is derived from the Kogge-Stone adder, reordering the cells to obtain a slice-based structure that allows an area-time effective serial implementation. It can be fed with parallel inputs and produce parallel outputs, differently from the digit-serial approach that results in the need for a data-formatter to convert a parallel input into digits, and to collect the digits of the output word. A standard-cell VLSI implementation for different values of N is presented: area-time performances are evaluated through circuit simulations, and compared with digit-serial adders with various digit-size, proving the attractiveness of the proposed structure.

A 380MHz, 150mW direct digital synthesizer/mixer in 0.25/spl mu/m CMOS

A direct digital frequency synthesizer/mixer IC processes two 12b quadrature inputs by providing two quadrature 13b outputs with a SFDR greater than 90dB and a frequency resolution of 0.088Hz at 380MHz clock frequency. The IC has an area of 0.22mm2 in 0.25mum CMOS and dissipates 150mW at 380MHz with a supply of 2.5V. At 1.8V, the power dissipation is 53mW at 270MHz

An area-efficient high-speed Reed-Solomon decoder in 0.25 /spl mu/m CMOS

In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 /spl mu/m CMOS technology, compares favourably with recently proposed RS decoders.

A reconfigurable 2D convolver for real-time SAR imaging

A novel architecture for real-time synthetic aperture radar signal processing that achieves real-time processing by using a recently proposed signum coded algorithm and time domain processing, is presented. New architecture is completely parallel and can be dynamically reconfigured in order to use different dimensions of data and filter matrices. A standard-cell VLSI implementation is presented and its performances are evaluated through circuit simulations.