D. Leung

0.1 /spl mu/m InGaAs/InAlAs/InP HEMT MMICs - a flight qualified technology

0.1 /spl mu/m InGaAs/InAlAs/InP HEMT MMIC technology on 3- inch InP substrates has been qualified in the categories of three-temperature lifetest, gamma radiation, RF survivability, electrostatic discharge, via-hole baking, and H/sub 2/ poisoning. The three-temperature lifetest (T/sub 1/ = 215/spl deg/C, T/sub 2/ = 230/spl deg/C and T/sub 3/ = 250/spl deg/C) of 0.1 /spl mu/m InGaAs/InAlAs/InP HEMT MMICs in a N/sub 2/ ambient demonstrates an activation energy (Ea) as high as 1.9 eV, achieving a projected median-time-to-failure (MTF) /spl ap/ 1/spl times/10/sup 8/ hours at a 125/spl deg/C junction temperature. Gamma radiation up to 5 mega RAD dose does not induce any degradation of DC/RF characteristics. Electrostatic discharge (ESD) shows destructive voltage up to 100 Volts. Furthermore, 0.1 /spl mu/m InP HEMTs exhibit less sensitivity to H/sub 2/ exposure than 0.1 /spl mu/m GaAs pseudomorphic HEMTs. The qualification results demonstrate the readiness of 0.1 /spl mu/m InGaAs/InAlAs/InP MMICs technology for flight applications.

Degradation mechanism and reliability improvement of InGaAs/InAlAs/InP HEMTs using new gate metal electrode technology

The degradation mechanism of 0.1 /spl mu/m InGaAs/InAlAs/InP HEMTs subjected to elevated temperature lifetest has been resolved with the techniques of scanning transmission microscope (STEM) and high-resolution energy-dispersive X-ray analysis (EDX). The results show that Schottky junction degradation is the dominant degradation mechanism, consisting of Ti inter-diffusion and In/sub 0.52/Al/sub 0.48/As Schottky barrier layer degradation. The degradation of the In/sub 0.52/Al/sub 0.48/As Schottky barrier exhibits the formation of TiAs/sub x/ and indium-rich In/sub 0.52+x/Al/sub 0.48/As and/or indium depleted In/sub 0.52-x/Al/sub 0.48/As under elevated temperature lifetest. The Schottky junction degradation mechanism can be alleviated by using a new gate metal electrode technology (NGMET), which exhibits superior reliability performance to that of the Ti/Pt/Au gate metal electrode. Moreover, InP HEMT MMICs using NGMET exhibit comparable RF performance to that of InP HEMT MMICs with Ti/Pt/Au gate metal. The results achieved here demonstrate the further enhancement of 0.1 /spl mu/m InP HEMT MMIC technology at Northrop Grumman Space Technology (NGST) using NGMET for military/space applications with high reliability performance requirement.

Tradeoff of DC/RF performance versus reliability in 0.1 /spl mu/m InP HEMTs

The tradeoff of DC/RF performance versus reliability has been explored on 0.1 /spl mu/m InP HEMTs. The tradeoff between performance and reliability shows the dependence on the process techniques. While higher performance could be achieved with certain process techniques, the reliability performance is adversely affected. Nevertheless, all the process variations explored here exhibit activation energy of approximately 1.9 eV. However, the time-to-failure (TTF) at lifetest temperatures of 230/spl deg/C and 250/spl deg/C and median-time-to-failure (MTTF) at junction temperature of 125/spl deg/C depend on the process techniques. The results are beneficial for balancing performance versus reliability through the adjustment of the processing technique.

High reliability of 0.07 /spl mu/m pseudomorphic InGaAs/InAlAs/InP HEMT MMICs on 3-inch InP substrates

The high-reliability performance of G-band (180 GHz) MMIC amplifiers fabricated using 0.07 pm T-gate pseudomorphic InGaAs/InAlAs/InP HEMTs on 3-inch wafers is reported. Low noise amplifiers were life-tested at two-temperatures (T/sub 1/ = 200/spl deg/C and T/sub 2/ = 215/spl deg/C) and stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2/spl times/10/sup 6/ hours at a channel temperature of 125/spl deg/C. MTTF was determined by 2-temperature constant current stress using |/spl Delta/G/sub mp/| > 20% as the failure criteria. This is the first demonstration of the high reliability of 0.07 /spl mu/m pseudomorphic InGaAs/InAlAs/InP HEMT MMICs on a 3-inch InP production process. This result demonstrates a robust 0.07 /spl mu/m pseudomorphic InGaAs/InAlAs/InP HEMT production technology for G-band applications.

High Performance and High Reliability of 0.1 /spl mu/m InP HEMT MMIC Technology on 100 mm InP Substrates

Uniform millimeter wave 0.1 mum InP HEMT MMICs (Ka-band, Q-band, W-band, and distributed amplifiers) on 100 mm InP substrates have been demonstrated. Moreover, high performance and high reliability have been achieved. The results indicate that the readiness of 100 mm InP HEMT technology for insertion to support military/space applications.

High reliability of 0.1 /spl mu/m InGaAs/InAlAs/InP HEMT MMICs on 3-inch InP substrates

The high-reliability performance of K-band MMIC amplifiers fabricated with 0.1 /spl mu/m gate length InGaAs/InAlAs/InP HEMTs on 3-inch wafers using a high volume production process technology is reported. Operating at an accelerated life test condition of Vds=1.5 V and Ids=150 mA/mm, two-stage balanced amplifiers were life tested at two-temperatures (T/sub 1/=230/spl deg/C, and T/sub 2/=250/spl deg/C) in nitrogen ambient. The activation energy (Ea) is as high as 1.5 eV, achieving a projected median-time-to-failure (MTF)>1/spl times/10/sup 6/ hours at a 125/spl deg/C junction temperature. MTF was determined by 2T constant current stress using |/spl Delta/S21|>1.0 dB as the failure criteria. This is the first report of high reliability 0.1 /spl mu/m InGaAs/InAlAs/InP HEMT MMICs based on small-signal microwave characteristics. This result demonstrates a reliable InGaAs/InAlAs/InP HEMT production technology.

High reliability non-hermetic 0.1 /spl mu/m GaAs pseudomorphic HEMT MMIC amplifiers

High reliability performance of a Q-band low-noise MMIC amplifier fabricated using 0.1 /spl mu/m production AlGaAs/InGaAs/GaAs HEMT process technology is reported. Operating at an accelerated DC bias condition of Vds=4.2 V and Ids=150 mA/mm, two-stage balanced amplifiers were lifetested at three temperatures (T/sub ambient/=255/spl deg/C, T/sub ambient/=270/spl deg/C, and T/sub ambient/=285/spl deg/C) in air ambient. After stress, MMIC amplifiers were brought down to room temperature and small-signal microwave characteristics were measured. Failure time for each temperature was determined using /spl Delta/S21=-1.0 dB measured at room temperature as the failure criteria. The activation energy (Ea) is 1.7 eV, achieving a projected median-time-to-failure (MTF) of 6/spl times/10/sup 9/ hours at a 125/spl deg/C junction temperature. This is the state-of-art of 0.1 /spl mu/m HEMT reliability based on S21 failure criteria of MMIC amplifiers under DC stress at high junction temperature in air ambient. This result demonstrates a robust HEMT technology which is immune to the stress effects of high electric field under high temperature operation, and demonstrates the suitability of the HEMTs for non-hermetic commercial applications.

Gate Sinking Effect of 0. 1 μm InP HEMT MMICs Using Pt/Ti/Pt/Au

Gate sinking effect of 0.1 mum InAlAs/InGaAs/InP HEMT MMICs (with Pt/Ti/Pt/Au gate metals) subjected to elevated temperature lifetests has been investigated. The results show that Pt sinking is the dominant degradation mechanism caused by Pt diffusing into the In0.52Al0.4As Schottky barrier layer. Pt sinking explains the observed evolutions of Schottky diodes, Ids-Gm transfer characteristics, and the S21 increase. Scanning-transmission-electron-microscope micrographs substantiate the alleviation of Schottky junction degradation of InP HEMTs using Pt/Ti/Pt/Au gates. Moreover, 2-temperature lifetest shows that the activation energy is approximately 1.55 eV, based on a failure criterion of DeltaIDSS = -20%. The results from this study demonstrate that Pt sinking is the primary degradation mechanism of 0.1 mum InP HEMT MMICs with Pt/Ti/Pt/Au gate metals

High reliability performance of 0.1-μm Pt-sunken gate InP HEMT low-noise amplifiers on 100 mm InP substrates

Accelerated temperature lifetesting at T<inf>channel</inf> of 240, 255, and 270 °C was performed on 0.1-μm Pt-sunken InP HEMT low-noise amplifiers fabricated on 100 mm InP substrates. The reliability performance was evaluated based on ΔS21 < −1 dB at 35 GHz. The lifetesting results exhibit activation energy of approximately 1.8 eV and lifetime projection of 99% reliability and 90% confidence exceeds 1×10⁸ hours at T<inf>channel</inf> of 125 °C. The high reliability demonstration of 0.1-μm Pt-sunken gate InP HEMT low-noise amplifiers on 100 mm InP substrates is essential for advanced military/space applications requiring high reliability performance.

The de-bias effect of gate current in InP HEMT MMICs

Increased gate current of InP HEMTs subjected to elevated temperature lifetest has been observed. The higher the temperature and the larger the gate periphery, the higher the gate current. On the other hand, gate resistors (Rg) are often used in the MMIC design for stability. As a result, the high gate current in conjunction with Rg de-biases the transistors in InP HEMT MMICs under elevated temperature lifetest. Accordingly, the evolution of DC parameters between discrete transistors and MMICs illustrates distinct difference. Furthermore, the de-bias effect of gate current in InP HEMT MMICs strongly depends on the lifetest temperature, gate periphery, and gate resistor. As a result, consideration of lifetest temperature, gate periphery, and gate resistors in InP HEMT MMICs is crucial in order to mitigate the de-bias effect induced by elevated temperature lifetest. In this paper, the de-bias effect of gate current in InP HEMT MMICs was illustrated for the first time.