R. Grundbacher

Cryogenic wide-band ultra-low-noise IF amplifiers operating at ultra-low DC power

This paper describes cryogenic broad-band amplifiers with very low power consumption and very low noise for the 4-8-GHz frequency range. At room temperature, the two-stage InP-based amplifier has a gain of 27 dB and a noise temperature of 31 K with a power consumption of 14.4 mW per stage, including bias circuitry. When cooled to 15 K, an input noise temperature of 1.4 K is obtained at 5.7 mW per stage. At 0.51 mW per stage, the input noise increases to 2.4 K. The noise measurements have been repeated at different laboratories using different methods and are found consistent.

Beyond G-band: a 235 GHz InP MMIC amplifier

We present results on an InP monolithic millimeter-wave integrated circuit (MMIC) amplifier having 10-dB gain at 235GHz. We designed this circuit and fabricated the chip in Northrop Grumman Space Technologys (NGST) 0.07-/spl mu/m InP high electron mobility transistor (HEMT) process. Using a WR3 (220-325GHz) waveguide vector network analyzer system interfaced to waveguide wafer probes, we measured this chip on-wafer for S-parameters. To our knowledge, this is the first time a WR3 waveguide on-wafer measurement system has been used to measure gain in a MMIC amplifier above 230GHz.

0.1 /spl mu/m InP HEMT devices and MMICs for cryogenic low noise amplifiers from X-band to W-band

We present the TRW 0.1 /spl mu/m InP HEMT MMIC production technology that has been developed and used for state-of-the-art cryogenic LNA applications. The 0.1 /spl mu/m InP HEMT devices typically show cutoff frequency above 200 GHz and transconductance above 1000 mS/mm. Aspects of device design and fabrication are presented which impact important parameters including the InP HEMT device gain, gate leakage current, and parasitic capacitance. One example of state-of-the-art cryogenic MMIC performance is a W-band cryogenic MMIC LNA operated at 20 degrees Kelvin that shows above 23 dB gain and a noise temperature of 30 to 40 K (0.45 to 0.6 dB noise figure) over the band of 80-105 GHz.

Physical identification of gate metal interdiffusion in GaAs PHEMTs

The Ti metal interdiffusion of Ti/Pt/Au gate metal stacks in 0.15-/spl mu/m GaAs PHEMTs subjected to high-temperature accelerated lifetest has been physically identified using scanning transmission electron microscopy. Further energy dispersive analysis with X-ray (EDX) analysis confirms the Ti diffusion into the AlGaAs Schottky barrier layer and the decrease of Schottky barrier height suggests the Ti-AlGaAs intermetallic formation, which is consistent with previous Rutherford backscattering spectroscopy/X-ray photoelectron spectroscopy studies. The Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus leading to a slight Gm increase, positive shift in pinchoff voltage, and S21 increase during the preliminary portion of the lifetest. Accordingly, the Ti interdiffusion effect implies that the lifetime of GaAs PHEMTs subjected to high-temperature accelerated lifetest could be dependent upon the initial thickness of the Schottky layer underneath the gate metal.

Reliability investigation of 0.07-μm InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In 0.75 Ga 0.25 As channel

The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.

0.1 /spl mu/m InGaAs/InAlAs/InP HEMT MMICs - a flight qualified technology

0.1 /spl mu/m InGaAs/InAlAs/InP HEMT MMIC technology on 3- inch InP substrates has been qualified in the categories of three-temperature lifetest, gamma radiation, RF survivability, electrostatic discharge, via-hole baking, and H/sub 2/ poisoning. The three-temperature lifetest (T/sub 1/ = 215/spl deg/C, T/sub 2/ = 230/spl deg/C and T/sub 3/ = 250/spl deg/C) of 0.1 /spl mu/m InGaAs/InAlAs/InP HEMT MMICs in a N/sub 2/ ambient demonstrates an activation energy (Ea) as high as 1.9 eV, achieving a projected median-time-to-failure (MTF) /spl ap/ 1/spl times/10/sup 8/ hours at a 125/spl deg/C junction temperature. Gamma radiation up to 5 mega RAD dose does not induce any degradation of DC/RF characteristics. Electrostatic discharge (ESD) shows destructive voltage up to 100 Volts. Furthermore, 0.1 /spl mu/m InP HEMTs exhibit less sensitivity to H/sub 2/ exposure than 0.1 /spl mu/m GaAs pseudomorphic HEMTs. The qualification results demonstrate the readiness of 0.1 /spl mu/m InGaAs/InAlAs/InP MMICs technology for flight applications.

A single chip 1-W InP HEMT V-band module

We present a world-record V-band single-chip InP HEMT power amplifier module. The two-stage amplifier consists of two channels with 4.48 mm total output periphery. It was fabricated using TRWs 0.5 /spl mu/m InP HEMT MMIC production process. The two channels were combined by off-chip Wilkinson combiners. Under CW test condition, the amplifier delivered 1 W of output power with 21% power added efficiency and 15 dB associated gain at 62 GHz. The linear gain was 20 dB. We have also characterized a single channel MMIC power amplifier which delivered 515 mW output power with 25% power added efficiency at 62 GHz.

A 150-215 GHz InP HEMT low noise amplifier with 12 dB gain

We present a 150-215 GHz InP HEMT MMIC with greater than 12dB gain across this band. The MMIC is a 3-stage, single-ended microstrip design implemented using 0.07 mum T-gate InP HEMT MMIC technology with 50 mum substrate

High performance and high reliability InP HEMT low noise amplifiers for phased-array applications

This paper describes the development of a Q-band low noise amplifier unit using a 0.1 /spl mu/m InP HEMT MMICs that has been demonstrated with high RF performance and high reliability over a frequency band from 43.5 to 45.5 GHz at Northrop Grumman Space Technology (NGST). The InP HEMT LNAs with high RF performance and high reliability are crucial for the advanced phased-array applications. The module demonstrates superior performance with gain greater than 30.1 dB and noise figure less than 3.2 dB over the frequency band of 43.5 to 45.5 GHz. The InP HEMT technology has an activation energy of 1.9 eV and mean-time-to-failure of 10/sup 8/ hours at T/sub junction/ of 125/spl deg/C and these MMICs further demonstrate the readiness of NGSTs 0.1 /spl mu/m InP HEMT MMICs technology for the advanced phased-array applications.

The effect of gate metal interdiffusion on reliability performance in GaAs PHEMTs

While Ti metal interdiffusion of Ti-Pt-Au gate metal stacks in GaAs pseudomorphic HEMT (PHEMTs) has been explored, the effect of Ti metal interdiffusion on the reliability performance is still lacking. We use a scanning transmission electron microscopy technique to correlate Ti-metal-InGaAs-channel-separation and Ti-sinking-depth with a threshold voltage V/sub T/. It has been found that Ti-sinking-depth is insensitive to V/sub T/. However, Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus affecting the I/sub dss/ degradation rate. Accordingly, we observe the dependence of /spl Delta/I/sub dss/ on V/sub T/. Devices with less negative V/sub T/ exhibit inferior reliability performance to those devices with more negative V/sub T/. The results provide insight into a critical device parameter, V/sub T/, for optimizing reliability performance based on I/sub dss/ degradation.