D. Lunardini

A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme

This paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip calibration circuit that allows the on-field reduction of the delay-line differential nonlinearity (DNL) down to values close to 1%. The cells are calibrated one by one in a serial way and the silicon area occupied by the calibration circuit is roughly the same as that occupied by the delay line itself. The prototype chips, realized with a 0.6-/spl mu/m CMOS technology, demonstrate the feasibility and effectiveness of the technique with a great reduction of the delay-line DNL. The nonlinearity calibration technique presented in this paper is of general use since the number and area of the shunt-capacitor configurable loads can be properly chosen according to the process mismatch parameters and the desired calibration range and resolution.

On the differential nonlinearity of time-to-digital converters based on delay-locked-loop delay lines

A theoretical analysis of the effects of the delay-line differential nonlinearity (DNL) on the typical performance parameters of high-resolution time-to-digital converters (TDCs) based on delay-locked-loop (DLL) delay lines has been developed. The theoretical study is based on the knowledge of the delay-line nonlinearity values that can be measured, with the desired precision, by means of a statistical code-density test. In particular, the effects on the TDC time resolution and error standard deviation curve as a function of the measured time interval are investigated. An a posteriori linearization technique, consisting in a proper correction of the TDC readouts, is then analyzed and its advantages are theoretically demonstrated. Finally, the theoretical results are superimposed on experimental data coming from a real TDC. The measured deviations from the ideal behavior are thus justified and can just be ascribed to the delay-line nonlinearity.

A high-resolution DLL-based digital-to-time converter for DDS applications

A Digital-to-Time Converter (DTC) based on a Delay-Locked Loop (DLL) for phase interpolation in Direct Digital Synthesis (DDS) applications is described. The conversion is made in two steps using digitally controllable delay cells with configurable shunt-capacitors load. The circuit is able to interpolate a 120 MHz clock, generating a delay proportional to an 8-bit digital control word with 32 ps resolution. The DDS system clock frequency is thus virtually enhanced up to about 30 GHz, achieving a strong reduction of the spurious component level. The 256 level interpolation is achieved using only 35 delay elements (excluding dummy cells).

A technique for nonlinearity self-calibration of DLLs

The on-chip nonlinearity self-calibration of a CMOS all-digital shunt-capacitor-based delay-locked delay-line is achieved by first measuring the nonlinearity of each delay-cell by means of a statistical test, and then individually correcting the cell delay mismatch according to the test results. An iterative calibration algorithm has been developed and a fully-digital circuit efficiently implementing the calibration procedure has been designed. Simulation results show the feasibility of the technique and a significant reduction of the delay-line maximum nonlinearity down to values that can be below 1%.

On-line calibration for non-linearity reduction of delay-locked delay-lines

A reduction of the non-linearity of a CMOS all-digital shunt-capacitor delay-line is achieved by performing an on-line statistical test of the line and correcting the individual cell delay mismatch according to the test results. A fully digital cell controller efficiently implementing the calibration procedure has been realized. Simulation results show the feasibility of the technique and the substantial reduction of the nonlinearity down to values lower then 1%.

A non-linearity self-calibration technique for delay-locked loop delay-lines

An on-chip non-linearity self-calibration of a CMOS all-digital shunt capacitor delay-line is achieved by first measuring the non-linearity of each delay-cell by means of a statistical test and then correcting the individual cell delay mismatch according to the test results. An iterative calibration algorithm has been developed and a fully digital circuit efficiently implementing the calibration procedure has been designed. The same digital controller is used to sequentially calibrate each delay-cell, so that the occupied silicon area is minimized. Simulation results show the feasibility of the technique and a substantial reduction of the maximum non-linearity down to values close to 1%.

60-channel high-resolution counter array for high-speed continuous long-term data acquisition

We present a fast and highly compact data acquisition system suitable for interfacing with photon-counter SPADA (single-photon avalanche diode array) sensors, which are used in state-of-art astronomical applications. The acquisition system features a 60-channel counter array, which is able to capture events with a rate of up to 20 MHz, and allows a continuous long-term data acquisition, lasting up to several hours, with a time resolution downto few tenths of microseconds at the same time. The system is based on a commercial-off-the-shelf (COTS) single board, allocating an FPGA and a DSP, connected by means of an IEEE 1394 high-speed serial link to a Linux box, which implements a TCP/IP server. Therefore, the acquisition parameters, as well as the collected data, can remotely be accessed through a LabView interface running on a different PC. A proof-of-concept demonstration has been realized and the experimental results are presented.

Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

We present a novel delay-locked loop (DLL) based architecture for multiphase clock generation with a time resolution finer than the gate delay. The basic idea consists in locking the delay line to a certain multiple of clock periods that is not fixed a priori, but is self-adjusted depending on process and operating conditions, and working frequency. In such a way, a wide locking range is achieved with a very compact delay cell structure. The circuit has been used to design a new TDC architecture in which a resolution (time-bin size) of about 16 ps is reached using a 0.35 mum CMOS technology. Post-layout simulations show the feasibility of the technique.