Roberto Roncella

Batteries and battery management systems for electric vehicles

The battery is a fundamental component of electric vehicles, which represent a step forward towards sustainable mobility. Lithium chemistry is now acknowledged as the technology of choice for energy storage in electric vehicles. However, several research points are still open. They include the best choice of the cell materials and the development of electronic circuits and algorithms for a more effective battery utilization. This paper initially reviews the most interesting modeling approaches for predicting the battery performance and discusses the demanding requirements and standards that apply to ICs and systems for battery management. Then, a general and flexible architecture for battery management implementation and the main techniques for state-of-charge estimation and charge balancing are reported. Finally, we describe the design and implementation of an innovative BMS, which incorporates an almost fully-integrated active charge equalizer.

Design and Verification of Hardware Building Blocks for High-Speed and Fault-Tolerant In-Vehicle Networks

This paper presents the design, implementation, and validation of a FlexRay transceiver and a SpaceWire (SpW) router and interface, which constitute the main hardware building blocks of the two in-vehicle communication standards. The FlexRay protocol features data rates up to 10 Mb/s and time- and event-triggered transmissions, along with scalable fault-tolerance support, and it is expected to become the standard network for X-by-wire and active safety automotive systems. However, collision avoidance and driver-assistance applications based on camera/radar sensors require data rates up to hundreds of megabits per second as well as fault tolerance, features that can hardly be covered by current or expected automotive standards. In this scenario, a promising technology seems to be the new SpW protocol, currently used in avionics and aerospace.

High-Efficiency Digitally Controlled Charge Equalizer for Series-Connected Cells Based on Switching Converter and Super-Capacitor

The charge stored in series-connected lithium batteries needs to be well equalized between the elements of the series. We present here an innovative lithium-battery cell-to-cell active equalizer capable of moving charge between series-connected cells using a super-capacitor as an energy tank. The system temporarily stores the charge drawn from a cell in the super-capacitor, then the charge is moved into another cell without wasting energy as it happens in passive equalization. The architecture of the system which employs a digitally-controlled switching converter is compared with the state of the art, then fully investigated, together with the methodology used in its design. The performance of the system is described by presenting and discussing the experimental results of laboratory tests. The most innovative and attractive aspect of the proposed system is its very high efficiency, which is over 90%.

A Digitally Controlled Shunt Capacitor CMOS Delay Line

Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 × 0.5ns delay under large temperature, supply voltage, and technological process quality variations.

Raman-based distributed temperature sensor with 1 m spatial resolution over 26 km SMF using low-repetition-rate cyclic pulse coding

We experimentally investigate the benefits of a new optical pulse coding technique for long-range, meter and submeter scale Raman-based distributed temperature sensing on standard single-mode optical fibers. The proposed scheme combines a low-repetition-rate quasi-periodic pulse coding technique with the use of standard high-power fiber lasers operating at 1550 nm, allowing for what we believe is the first long-range distributed temperature measurement over single-mode fibers (SMFs). We have achieved 1 m spatial resolution over 26 km of SMF, attaining 3°C temperature resolution within 30 s measurement time.

A Novel Bit-Level Systolic Array Median Filter

This paper presents examples of the application of ethopharmacology to the study of aggression. Low doses of benzodiazepines may increase aggression under appropriate conditions. In various animal models in male and female rats and mice the aggression enhancing effects are particularly marked when aggression is inhibited by internal or external events. It is therefore suggested that benzodiazepines have no direct effect on aggression, but modulate inhibitory factors which regulate aggression.

A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme

This paper describes a CMOS 32-tap delay-locked delay line, realized with a shunt-capacitor circuit scheme, with an on-chip calibration circuit that allows the on-field reduction of the delay-line differential nonlinearity (DNL) down to values close to 1%. The cells are calibrated one by one in a serial way and the silicon area occupied by the calibration circuit is roughly the same as that occupied by the delay line itself. The prototype chips, realized with a 0.6-/spl mu/m CMOS technology, demonstrate the feasibility and effectiveness of the technique with a great reduction of the delay-line DNL. The nonlinearity calibration technique presented in this paper is of general use since the number and area of the shunt-capacitor configurable loads can be properly chosen according to the process mismatch parameters and the desired calibration range and resolution.

Enhanced model for Lithium-Polymer cells including temperature effects

An accurate model of the elementary accumulation device is fundamental for sizing and controlling the battery pack to be used in electric and hybrid vehicles. Indeed, the implementation of such a model within the Battery Management System makes it possible to evaluate the status and the behavior of the battery pack in every condition and to apply a correct control strategy. This work shows the characterization and modeling of a commercial Lithium-Polymer cell, which properly considers thermal effects on cell behavior. The specific designed thermostatic chamber is described and the experimental results are presented and compared to those simulated with the developed model.

A 250-ps time-resolution CMOS multihit time-to-digital converter for nuclear physics experiments

This paper presents a CMOS realization of a time-to-digital converter (TDC) for nuclear physics experiments. An innovative and robust architecture, already used in a previous TDC version with 1 ns of bin size, has been adopted and improved with the aim to achieve a 500-ps bin size. The TDC has eight input channels plus a common channel. It can store up to 32 events per channel with a double-hit resolution of 8 ns. It can realize common-start and common-stop operations. It has 4.2 ms of input range with a 125-MHz system clock. The chip uses an asynchronous interpolator system based on a delay-locked line to increase the coarse resolution. It has been fabricated in a double-metal single poly n-well, 1-/spl mu/m CMOS process with an area of about 77 mm/sup 2/. Measurements show that the TDC has better performance compared to similar devices, especially the time resolution below 250 ps.

Multihit multichannel time-to-digital converter with /spl plusmn/1% differential nonlinearity and near optimal time resolution

An eight-channel, 1 ns bin-size, 23 b dynamic range, single-chip, multihit, time-to-digital converter (TDC) is presented in this paper. A new architecture mixing two previous TDC realizations has been adopted. The chip can execute common-start or common-stop operations on the trailing, leading, or both transitions of the input channels; it stores at least 32 events/channel with a double-hit resolution of 16 ns. A prototype of about 120 mm/sup 2/ has been integrated into a double-metal, single-poly, n-well 1 /spl mu/m CMOS process, and its performance has been compared to that of similar devices. Test results show that a differential nonlinearity error of /spl plusmn/1%, an integral nonlinearity less than 0.2 least significant hit (LSB), and a time resolution of 0.443 LSB-significantly better than those of comparable TDCs and very close to the theoretical limit of 0.408 LSB-have been achieved.