D. Ney

Managing SRAM reliability from bitcell to library level

Static Random Access Memories (SRAMs) are present nowadays in all CMOS products in large quantities. Besides, they are often very challenging both on process side (due to small dimensions) and on design side (due to performance request). As a consequence, managing their reliability is of prime importance, though it is quite complex due to their overall complexity. This paper demonstrates a full reliability-based design flow for SRAM libraries including both Front-End degradation modes (NBTI, PBTI and HCI) as well as Back-End degradation modes (Electromigration). Large experimental datasets on various technologies and SRAM bitcells have been used all along the paper to show clear Silicon-CAD correlation evidences, demonstrating the efficiency and accuracy of the developed flow.

Effect of Joule heating on the determination of electromigration parameters

The use of accelerated electromigration (EM) wafer level reliability (WLR) tests aims at performing tests on a large sample size faster than at package level (PLR). Meanwhile, the correlation of times to failure determined from package level tests and wafer level tests is sometimes not obvious. Therefore, little trust is put in extrapolated lifetime determined from WLR tests. To elucidate this apparent inconsistency, we developed a lifetime model, based on the flux divergence under high thermal gradient at the end of EM line. We found an apparent evolution of the current density exponent n from 1.5 to 2.1 due to the coupling between current density and temperature in WLR test. Besides, no important change of the activation energy Ea is found.

Dynamics of Resistance Evolution During Electromigration

The careful analysis of resistance evolution with time during electromigration tests provided valuable information about damascene architecture and intrinsic electromigration behaviour. We found first, that resistance evolution includes an abrupt event, the amplitude of which is usually corresponding to the failure criteria and second, that the height of this step (and sample resistance) is correlated with time to fail. We showed that the evolution of time to step was more likely to be due to the vertical growth of a void which length is making resistance step amplitude varying from sample to sample. Second we found a correlation between sample initial resistance and time to failure that is believed to be due to trench depth. However this effect is widely spread and correlation coefficient is as low as 0.3. These 2 phenomena combined together, increase the standard deviation affecting lifetime. As a matter of fact, resistance increase rate is expected to be directly proportional to void growth rate and copper diffusion coefficient whereas step height is function of the void shape and barrier thickness

Electromigration induced void kinetics in Cu interconnects for advanced CMOS nodes

Time evolution of resistance during EM tests is extensively analyzed for various Cu interconnect structures and processes from the 40 nm node technology. Resistance evolution is used to model void nucleation and growth kinetics. We show that adding Al or other impurities in the line is effective to increase electromigration lifetime. This lifetime increase is due, as expected, to Cu drift velocity decrease but also to an increase of the time to void formation. TEM picture shows that Al precipitates are formed at grain boundaries and are most likely responsible for the occurrence of an incubation time Resistance saturation is observed for short lines thanks to Blech effect. A resistance model is developed to characterize short length effect in 40 nm node. The model is also used to explain EM lifetime improvement thanks to a pre-stress condition where compressive stress is added at cathode end of long line structures.

Effect of reservoir on electromigration of short interconnects

As the interconnect cross-sections are ever scaled down, a particular care must be taken on the tradeoff between increase of current density in the back end of line and reliability to prevent electromigration (EM). Some lever exists as the well-known Blech effect [1]. One can take advantage of the EM induced backflow flux that counters the EM flux. As a consequence, the total net flux in the line is reduced and additional current density in designs can be allowed in short lines. However, the immortality condition is most of the time addressed with a standard test structures ended by two vias [2]–[3]. Designs present complex configurations far from this typical case and the Blech product (jL)c can be deteriorated or enhanced [4]. In the present paper, we present our study of EM performances of short lines ended by an inactive end of line (EOL) at one end of the test structure. Significant differences on the median time to failure (MTF) are observed with respect to the current direction, from a quasi deletion of failure to a significant reduction of the Blech effect. Based on the resistance saturation, a method is proposed to determine effective lengths of inactive EOL configurations corresponding to the standard case.

Electromigration threshold in copper interconnects and consequences on lifetime extrapolations

Electromigration in interconnects is a major reliability concern for integrated circuits, which leads to aggressive design rules. These rules can be lightened by taking advantage of the Blech effect in extrapolated lifetimes. In the present paper is reported the critical product (jL)/sub c/ for copper-oxide interconnects measured at 250/spl deg/C, 300/spl deg/C and 350/spl deg/C from electron-migration lifetime tests. The existence of this threshold product implies an increase of n values from Blacks model with decreasing (current density-line length) products. This increase significantly changes the extrapolated lifetime at operating conditions.

Determination of the acceleration factor between wafer level and package level electromigration test

The characterization and monitoring of electromigration performance is usually performed using wafer level or package level tests. These two types of test involve very different temperature gradient and current density conditions. These differences of stress condition may affect the determination of electromigration parameters, namely the activation energy, Ea, and the current exponent, n, as described in the empirical Blacks law: MTF = A.j/sup -n/exp(Ea/kT). The apparent evolution of n and Ea is critical because it complicates the calculation of extrapolated lifetime. To elucidate this apparent inconsistency, we built a numerical model of the flux of matter in a copper line to simulate lifetime and acceleration factor corresponding to wafer and package level electromigration tests. Our numerical model is able to simulate TTF corresponding to electromigration tests on a wide range of current density (two orders of magnitude). The analysis of simulated TTF predicts that the error in Blacks law parameters Ea and n may occur both from wafer level (high current density and Joule heating) and package level (low current density). As a consequence, we recommend taking into consideration temperature gradients as well as the Blech effect to extrapolate lifetime correctly.

Microstructure local effect for electromigration reliability improvement and Cu damascene lines design rules relaxation

Implication of microstructure during electromigration void formation process is studied in this paper. Dual damascene Cu lines with cathode end width variations are characterized. The idea of these variations being to force different microstructure profiles within the same test structure. The narrow-to-wide (NTW) width transition structure shows better electromigration performances than usual structure with a constant width (CW) along the line length. Bamboo Cu grains in the NTW structure wider segment are evidenced to slow down Cu atoms migration, inducing a local Blechs-like effect. This results in delayed void nucleation time and reduced void growth rate leading to increased lifetime. By this study, we show how great advantage can be taken on lifetime with this new design.

Redundancy method to assess electromigration lifetime in power Grid design

The tendency of semiconductor market to increase component density in small chip leads to reliability issues such as Electromigration (EM). This phenomenon becomes critical in deep submicron design technology. In this paper we assess chip power grid lifetimes by taking into account redundant paths contribution in case of EM degradation. The application of this method for wire lifetime validation of a 32nm microprocessor has reduced significantly wires susceptible to EM given by simulation tools.

Improved statistical analysis at low failure rates in Cu electromigration using an innovative multilink test structure

An innovative electromigration test structure is described in this paper. This new structure consisting of serial connected links is designed to address very early percentiles of lognormal electromigration failure time distribution and highlight extrinsic failures. The simplicity of implementation, data treatment and the correlation with elemental dual damascene test lines make this structure a pretty good candidate for the future of interconnects reliability.