X. Federspiel

Extensive analysis of resistance evolution due to electromigration induced degradation

Electromigration failure kinetic has been studied with resistance evolution versus time of interconnects during degradation. Tests were performed on dual damascene copper lines, issued from the 65 nm technology node, of various widths and lengths. All samples exhibit similar resistance evolution: an initial step, characterized by its height called Rstep, follows a linear kinetic characterized by its slope called Rslope. These two parameters were systematically extracted; Rstep is proportional to the critical volume of a void spanning the whole section of the line, and Rslope to the copper drift velocity. On one hand, the linewidth does not affect these two parameters. On the other hand, Rslope is highly dependent on the line length because of the Blech effect, while Rstep remains constant. Consequently, it was demonstrated that the classical linear function L/TTF=f(jL), where TTF is the time to failure, j is the current density, and L is the line length, used to study the Blech effect in interconnects cou...

Stress-induced electromigration backflow effect in copper interconnects

The electromigration threshold in copper interconnect is reported in this paper. The critical product (jL)c is first determined for copper oxide interconnects with temperature ranging from 250degC to 350degC from package-level experiments. It is shown that the product does not significantly change in this temperature range. Then, (jL)c was extracted for copper low-k dielectric (k=2.8) interconnects at 350degC. A larger value than that for oxide dielectric was found. Finally, a correlation between the n values from Blacks model and with jL conditions was established for both dielectrics

Use of Resistance-Evolution Dynamics During Electromigration to Determine Activation Energy on Single Samples

In this paper, we present an analysis of resistance change events that are occurring during the degradation of interconnects. The events analyzed are the following: 1) a step jump in resistance and 2) a subsequent progressive linear increase of resistance. We first find that the height of the step is correlated with time to fail. We show that the occurrence of a step is likely due to the vertical growth of a void, and the variation of the resistance-step amplitude is due to the variation of the length of the void from sample to sample. We then find that resistance-increase rate of the progressive part is correlated with copper drift velocity. Thus, we show that it is possible to determine an activation energy on every sample, which is performing temperature change during the progressive part of the resistance increase.

Effect of Joule heating on the determination of electromigration parameters

The use of accelerated electromigration (EM) wafer level reliability (WLR) tests aims at performing tests on a large sample size faster than at package level (PLR). Meanwhile, the correlation of times to failure determined from package level tests and wafer level tests is sometimes not obvious. Therefore, little trust is put in extrapolated lifetime determined from WLR tests. To elucidate this apparent inconsistency, we developed a lifetime model, based on the flux divergence under high thermal gradient at the end of EM line. We found an apparent evolution of the current density exponent n from 1.5 to 2.1 due to the coupling between current density and temperature in WLR test. Besides, no important change of the activation energy Ea is found.

Electromigration multistress pattern technique for copper drift velocity and Black’s parameters extraction

Package electromigration tests were performed on dual damascene copper interconnects issued from the 90, 65 and 45 nm-node technologies. By varying the stress conditions during the steady state regime of the resistance increase, we study drift velocity evolution as a function of the current density j. Thus we show some large deviation of the Blacks law, which assumes a linear dependence of the lifetime with j. Finally we have determined the Blacks exponent n in a broad range of current density j (2.5-50 mA/mum2). For 250 mum long lines, a n=1 is obtained between 10 and 20 mA/mum2, it increases up to 2 for j=2.5 mA/mum2.

Use of bidirectional current stress for in depth analysis of electromigration mechanism

Electromigration under bidirectional current is studied on dual damascene copper interconnects for the 65 nm node. Physical analyses confirm void location a both ends of the line and copper transport over long distance. Resistance evolution was studied and correlated to void healing/growth kinetics. Finally, we show the interest of bidirectional tests to study multimodal failure mode.

Correction of Self-Heating for HCI Lifetime Prediction

Self-heating (SH) effects, observed during the development of SOI technology for high performance circuits, raise questions concerning the validity of the extrapolation method used for hot carrier injection (HCI). The integration of buried oxide, with low thermal conductivity, enhances self-heating (SH) in MOS transistor devices submitted to DC HCI stress, and leads to potential erroneous HCI lifetime prediction. In this paper, the authors propose a new methodology for the lifetime prediction based on DC HCI stress for SOI technology. The SH is quantified using coupled DC HCI stress and gate resistance measurements, for different transistor widths (W). Then, the degradation part due to SH is removed enabling accurate HCI lifetime prediction.

A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability in static random access memory (SRAM) cells. This measurement procedure is based on the supply read retention voltage metric. The variability results obtained with this technique are explained by means of Monte Carlo SPICE simulations. The analytical model is then proposed to extrapolate this BTI-induced variability at different stress conditions. Finally, the impact of this variability on a large SRAM array is investigated. A semianalytical method is first developed to calculate the fresh read failure probability for different operating voltages VDD. The model is then extended to address the effect of BTI stress on the SRAM array. Results show that under SRAM cells operating conditions the bitcell read stability is barely impacted by BTI stress even after 10 years of work.

Determination of the acceleration factor between wafer level and package level electromigration test

The characterization and monitoring of electromigration performance is usually performed using wafer level or package level tests. These two types of test involve very different temperature gradient and current density conditions. These differences of stress condition may affect the determination of electromigration parameters, namely the activation energy, Ea, and the current exponent, n, as described in the empirical Blacks law: MTF = A.j/sup -n/exp(Ea/kT). The apparent evolution of n and Ea is critical because it complicates the calculation of extrapolated lifetime. To elucidate this apparent inconsistency, we built a numerical model of the flux of matter in a copper line to simulate lifetime and acceleration factor corresponding to wafer and package level electromigration tests. Our numerical model is able to simulate TTF corresponding to electromigration tests on a wide range of current density (two orders of magnitude). The analysis of simulated TTF predicts that the error in Blacks law parameters Ea and n may occur both from wafer level (high current density and Joule heating) and package level (low current density). As a consequence, we recommend taking into consideration temperature gradients as well as the Blech effect to extrapolate lifetime correctly.

Blech effect in dual damascene copper-low k interconnects

The electromigration threshold in copper interconnect is reported in this study. The critical product jLc was first determined for copper-oxide interconnects in the temperature range 250/spl deg/C-350/spl deg/C from package level experiments. It is shown that the product does not significantly change in this temperature range. Then jLc was extracted for copper-low k dielectric (k=2.8) interconnects at 350/spl deg/C. A larger value than for oxide dielectric was found. Finally, a correlation between n values from Blacks model and jL conditions was established for both dielectrics.