D. Pawlik

Benchmarking and improving III-V Esaki diode performance with a record 2.2 MA/cm 2 peak current density to enhance TFET drive current

III-V tunneling field effect transistors (TFET) for low voltage logic applications (<;0.5V) have gained attention with the demonstration of sub-60 mV/dec. subthreshold slopes [1]. A key outstanding issue with TFETs is limited drive currents, due to non-optimized carrier tunneling. With that issue in mind, the aim of this work is to map III-V Esaki tunnel diode (TD) performance to engineer TDs with ultra high current densities while maintaining large peak-to-valley current ratios (PVCR). This work describes the most comprehensive experimental benchmarking of TD performance reported, including (i) GaAs, (ii) In0.53Ga0.47As, (iii) InAs, (iv) InAs0.9Sb0.1/Al0.4Ga0.6Sb, and (v) InAs/GaSb as a function of doping and effective tunnel barrier height. These results confirm that heterojunctions (bandgap engineering) and doping will enhance peak (JP) and Zener current densities beyond homojunction TDs [3], to a record 2.2MA/cm2 (JP) and 11 MA/cm2 (@ -0.3 V), laying the fundamental groundwork for a III-V TFET at the 7 nm technology node.

Benchmarking current density in staggered gap In0.53Ga0.47As/GaAs0.5Sb0.5 heterojunction Esaki tunnel diodes

The impact of dopant concentration on the current densities of In0.53Ga0.47As/GaAs0.5Sb0.5 heterojunction Esaki tunnel diodes is investigated. Increased doping density results in increased peak and Zener current densities. Two different structures were fabricated demonstrating peak current densities of 92 kA/cm2 and 572 kA/cm2, Zener current densities of 994 kA/cm2 and 5.1 MA/cm2 at a −0.5 V bias, and peak-to-valley current ratios of 6.0 and 5.4, respectively. The peak current scaled linearly with area down to a 70 nm diameter. The peak current densities were benchmarked against Esaki diodes from other material systems based on doping density and tunnel barrier height.

Record PVCR GaAs-based tunnel diodes fabricated on Si substrates using aspect ratio trapping

High quality, low defect GaAs virtual substrates on Si, produced by the aspect ratio trapping growth technique, have been used for the fabrication of n+GaAs/n+InGaAs/p+GaAs Esaki diodes. All epitaxial layers were grown by reduced-pressure chemical vapor deposition/metalorganic chemical vapor deposition , instead of the molecular beam epitaxy technique commonly used for most high performance Esaki diodes. Four Esaki diode structures were fabricated and measured, with current densities up to 1 kA/cm2. Peak-to-valley current ratios up to 56 have been achieved, which is greater than twice that of the best GaAs Esaki diodes previously reported.

Full Band Atomistic Modeling of Homo-junction InGaAs Band-to-Band Tunneling Diodes Including Band Gap Narrowing

A homo-junction In0.53Ga0.47As tunneling diode is investigated using full-band, atomistic quantum transport approach based on a tight-binding model (TB) and the non-equilibrium Green’s function formalism. Band gap narrowing (BGN) is included in TB by altering its parameters using the Jain-Roulston model [S. C. Jain and D. J. Roulston, Solid-State Electron. 34, 453 (1991)]. BGN is found to be critical in the determination of the current peak and the second turn-on in the forward bias region. Empirical excess current that mimics additional recombination paths must be added to the calculation to model the diode behavior in the valley current region. Overall, the presented model reproduces experimental data well.

Implications of record peak current density In 0.53 Ga 0.47 As Esaki tunnel diode on Tunnel FET logic applications

Inter-band tunnel field effect transistors (TFETs) have recently gained a lot of interest because of their ability to eliminate the 60mV/dec sub-threshold slope (STS) limitation in MOSFET. This can result in higher I<inf>ON</inf>-I<inf>OFF</inf> ratio over a reduced gate voltage range, thus predicting TFETs superior for low supply voltage (V<inf>DD</inf> ≤ 0.5V) operation. Unlike Si and Ge, III-V semiconductors like In<inf>0.53</inf>Ga<inf>0.47</inf>As have smaller tunneling barrier and tunnelling mass, thus making them a design choice to eliminate drive current (I<inf>ON</inf>) limitations in TFETs [1–2]. In this work, (i) we present the experimental demonstration of record peak current density (J<inf>PEAK</inf>) In<inf>0.53</inf>Ga<inf>0.47</inf>As Esaki tunnel diode, formed using MBE grown in-situ doped epitaxial layers [4]. (ii) Using a non-local tunneling model in Sentaurus device simulator [3], the measured current-voltage characteristics (J-V) is modeled and the model parameters are calibrated. (iii) Novel In<inf>0.53</inf>Ga<inf>0.47</inf>As ultra thin body (7nm)-double gate-TFET (UTB-DG-TFET) design to boost I{ON} is discussed using the calibrated non-local tunneling model. (iv) Pulse transient response of the novel In<inf>0.53</inf>Ga<inf>0.47</inf>As TFET inverter is presented and compared with Si based MOSFET inverters at a supply voltage of 0.5V.

Performance Evaluation of In 0.53 Ga 0.47 As Esaki Tunnel Diodes on Silicon and InP Substrates

In_0.53Ga_0.47As Esaki tunnel diodes grown by molecular beam epitaxy on an Si substrate via a graded buffer and control In_0.53Ga_0.47As Esaki tunnel diodes grown on an InP substrate are compared in this paper. Statistics are used as a tool to show peak-to-valley ratio for the III-V on Si sample and the control that perform similarly below 8.6 × 10^-10 cm^-2. The existence of a critical device area suggests the potential to utilize III-V on Si for other deeply scaled tunnel devices.

Sub-micron Esaki Tunnel Diode fabrication and characterization

Recently much effort has been made in characterizing and realizing tunneling field effect transistors (TFET). Fundamental to the operation of such devices is the direct band-to-band tunneling of carriers from the n++ source to the p++ drain, which is the same current transport mechanism of Esaki Tunnel Diodes (ETD). Therefore, ETDs are an effective way to understand the potential of TFETs for high speed, low power applications. Recently, Rommel, et al. [1] reported on record breaking GaAs/InGaAs ETDs fabricated on Si substrates, with additional analysis by Pawlik, et al. [2]. However, these studies have been performed on large size devices with junction areas in excess of 5 μm2. Few studies of sub-micron ETDs have been performed [3], which is critical for integration of TFETs into modern VLSI/UVLSI circuits. This abstract reports on the fabrication and characterization of sub-micron GaAs/InGaAs ETDs on a Si substrate with junction areas below 0.1 μm2.

High Temperature Characterization of Si/SiGe Resonant Interband Tunnel Diodes

Co-integration of Si-based tunnel diodes and CMOS circuits has been proposed for several years as a means to lower power consumption, reduce operating voltage and shrink device count. Recently, the successful integration of Si/SiGe resonant interband tunnel diodes [1,2] with CMOS [3] was demonstrated with room temperature operation. However, integrated circuits realistically operate significantly above room temperature, usually around 373K. Therefore, SPICE models used by circuit designers must account for device performance variations due to temperature changes ranging from 300K to 473K. For circuit applications, the key tunnel diode parameters are the peak and valley current densities (Jp and Jv, respectively) as well as the peak-to-valley current ratio (PVCR). Previous high temperature studies on Si-based Esaki diodes [4-6] and Si/SiGe resonant interband tunnel diodes (RITD) [7] showed some dissimilar trends for PVCR. This study examines the high temperature operation of Si/SiGe RITD more closely up to 473K. Figure 1 illustrates the schematic diagram of the various RITD structures investigated in this study. The intrinsic layer between the δ-doped planes consists of X nm of undoped Si and Y nm of undoped SiGe. Three different structures with 1nm/3nm, 2nm/4nm, and 4nm/4 nm of X/Y i-layer thicknesses, named TD-A, TD-B, and TD-C, respectively were fabricated using low temperature molecular beam epitaxy. The current-voltage characteristics of these devices were measured using a Keithley 4200 Semiconductor Parameter Analyzer. The temperature of the heat chuck was controlled via an ΩE Omega CSC32-J bench top controller. A thermocouple was mounted in direct contact with the wafer for all measurements. Initial measurements were taken at room temperature, with subsequent readings in 10K increments from 300K to 473K. Several measurements were also taken while the wafer was cooling down. Those results were consistent with the initial heat up measurements. The I-V characteristics were not found to vary significantly over a two hour time period for any particular temperature. Figure 2 shows the I-V characteristics for device TD-C. The general shape of the curve remains the same over the entire temperature range. Figure 3 overlays valley currents normalized with respect to the room temperature valley current for TD-C as well as data from other published studies [5-7]. It should be noted that the normalized Jv data for TD-A and TD-B directly overlays TD-C and Jin’s data [7]. Si/SiGe RITD valley current shows a weak temperature dependent signature. In contrast Esaki diodes formed by proximity annealing [5,6] exhibit a stronger temperature sensitivity. As illustrated in Fig. 4, the PVCR of TD-A, TD-B, and TD-C decreases as temperature increases. Device TD-A has a PVCR of 1.99 at 373 K. However, devices TD-B and TD-C resulted in PVCRs of 2.58 and 2.91 at 373 K, respectively. Overall, there was no significant effect on the device characteristics from heating the Si/SiGe RITDs. The PVCRs observed at 373 K were found to be sufficient for digital circuit/memory circuit operation. These results conclusively demonstrate that high temperature operation will not be a limiting factor in CMOS/RITD circuitry.

Analysis of the Biasing Conditions and Latching Operation for Si/SiGe Resonant Interband Tunnel Diode Based Tunneling SRAM

A memory cell utilizing negative differential resistance (NDR) characteristic of tunnel diodes was first proposed by Goto et al. in 1960 [1]. The inherently fast tunneling phenomenon and low power consumption makes this type of memory architecture attractive. Combined with the possibility for vertical integration of the tunnel diode directly atop of the source/drain region of the FET, a compact design can be achieved. The concept was further refined by Van der Wagt et al. to achieve low stand-by power by utilizing diode junction capacitance to lower peak and valley current densities. Utilizing InP/InGaAs resonant tunnel diode (RTD), a nA operation was realized [2]. The realization in Si-based system, however, is still limited. Utilizing pSi/oxynitride/npoly Si tunnel diodes, Morimoto et al. demonstrated a low voltage T-SRAM [3]. The performance was limited by the poor performance of the tunnel diode and the lack of capability to scale current density and size. In recent work by the authors, Si/SiGe resonant interband tunnel diodes (RITDs) have been successfully integrated with CMOS devices. A low voltage monostable-bistable logic element (MOBILE) latch has been demonstrated [4]. The current density of a Si/SiGe RITD is controlled by adjusting the SiGe i-layer thickness, making it suitable for circuit integration with CMOS [5]. In this work, Si/SiGe RITD-based T-SRAM cell is bread-boarded and its latching mechanisms have been investigated extensively. As shown in Fig. 1(a), each T-SRAM cell consists of two tunnel diodes connected in series with a current manipulator, NFET, connected into the sense node. In this experiment, Si/SiGe RITDs with 6 nm i-layer grown on top of p implanted wells with PVCR of 2.25 and peak current density of 2.15 kA/cm were used. During the stand-by (SB) mode, NFET is off, and VDD is fixed at 1.0V, as illustrated in Fig. 1(b). RITD1 and RITD2 function as the driver and load, respectively, resulting in folded currentvoltage characteristics as depicted in Fig. 2. The intersections the drive and load curves indicate two stable latching states, stand-by low (SBL) and high (SBH) at 246 mV and 746 mV, respectively. These two states represent logic low and high, respectively. It is important to note that the intersection at the negative differential resistance (NDR) region is unstable and is not be used as a latching point. To latch into logic high, a current has to be supplied into the sense node through the NFET by applying a bias of 2.0V to both the drain and gate. Fig. 1(c) depicts the circuit diagram during this write high (WH) cycle. By activating the NFET, a current path parallel to RITD2 is formed, elevating the overall current that passes through the load diode as shown in Fig. 3. At the same time, current injection into the middle node also causes a decrease in drive current. As a result, the potential at the sense node (VSN) changes abruptly from point A, 246 mV, to B, 802 mV. By restoring the stand-by biasing conditions, i.e. shut-off the NFET, VSN restores to the nearest stable latching state at 746 mV, point C. In the write to logic low (WL) cycle, current is subtracted or drained from the sense node by simply applying a bias to the gate of the NFET and grounding the bit node. Since there is a potential difference between sense and bit node, current will flow out of the sense node as illustrated in Fig. 1(d). In other words, a current path parallel to RITD1 is created, causing a rise in the drive current. Unlike the write high cycle, the load characteristic is undisturbed during WL cycle. As a result, VSN changes suddenly from point C, 746 mV, to D, 199 mV (Fig. 4). Restoration to the stand-by conditions shifts the latching point back to A, 246 mV. The corresponding time diagram of write and read cycles is given in Fig. 5. Slight discrepancies between the values from I-V curves and transient diagram is due to parasitic resistance present in the test setup. In conclusion, a prototype of Si/SiGe RITD-based T-SRAM has been presented. Load line analysis is performed to understand the latching mechanisms during the write and read cycles. This demonstration will lead to realization of fully-integrated Si/SiGe RITD/NMOS T-SRAM. Ultra-low power tunneling SRAM can be achieved by utilizing low current density RITDs.

Germanium on Nothing for Nanowire Devices

Advances in crystal growth techniques are enabling novel structures and nanowire (NW) devices which show promise across a wide array of applications such as CMOS, photo and chemical detectors, as well as light emission; however, integrating these NWs into a circuit is nontrivial [1-4]. NW growth processes can produce varying crystal orientations of the NWs and random placement on the substrate/contact surface complicates the process [1, 3, 4]. Some groups have utilized reactive ion etching (RIE) of a film stack of Si/SixGe1-x combined with wet etching to produce Si NWs on a substrate and, in principle, similar techniques could be adapted for Ge NW systems In this study, the authors will present on the advancements made on the Germanium on Nothing (GON) technology reported previously Figure 1 [5].