Stephen Sudirgo

Diffusion barrier cladding in Si/SiGe resonant interband tunneling diodes and their patterned growth on PMOS source/drain regions

Si/SiGe resonant interband tunnel diodes (RITDs) employing /spl delta/-doping spikes that demonstrate negative differential resistance (NDR) at room temperature are presented. Efforts have focused on improving the tunnel diode peak-to-valley current ratio (PVCR) figure-of-merit, as well as addressing issues of manufacturability and CMOS integration. Thin SiGe layers sandwiching the B /spl delta/-doping spike used to suppress B out-diffusion are discussed. A room-temperature PVCR of 3.6 was measured with a peak current density of 0.3 kA/cm/sup 2/. Results clearly show that by introducing SiGe layers to clad the B /spl delta/-doping layer, B diffusion is suppressed during post-growth annealing, which raises the thermal budget. A higher RTA temperature appears to be more effective in reducing defects and results in a lower valley current and higher PVCR. RITDs grown by selective area molecular beam epitaxy (MBE) have been realized inside of low-temperature oxide openings, with performance comparable with RITDs grown on bulk substrates.

NMOS/SiGe Resonant Interband Tunneling Diode Static Random Access Memory

Tunneling-based static random access memory(SRAM)has been sought as a viable solution for a lowpower and high speed embedded memory application. The first cell design, proposed by Goto et al. [1],consists oftwotunnel diodes connected in series, oneacting as the drive andthe other as the load as showninFig. 1. This configuration allows for bistable operation at a particular range ofsupply voltages (VDD). Theinformation is stored at the sense node, whichcanbe altered by modulating current into the node via a FET.Byinjecting a current into the sense node, the cell is forced to latch to a high state as illustrated in Fig l(b).During write low operation, the FETis used to discharge the cell, pulling the sense node potential to a lowstate as depicted in Fig l(c). The demonstration ofthis type of bistable latch has been done in the Ill-Vmaterial system, showing avery promisingperformance bothin speedandpowerdissipation [2]. Morimotoetal. realizedthe systemin Si

Monolithically integrated Si/SiGe resonant interband tunneling diodes/CMOS MOBILE latch with high voltage swing

The Si/SiGe RITDs grown by MBE have been monolithically integrated with CMOS for the first time. The integrated devices resulted in a PVCR (peak-to-valley current ratio) of 2.8 at room temperature, showing promise towards the realization of RITD/CMOS circuitry. A RITD-NMOS MOBILE latch has been demonstrated in Si. This logic element enables digital and ternary circuit design for high density storage. The I-V characteristics of the integrated CMOS/RITD devices and I/sub D/-V/sub D/ characteristics of NMOS and PMOS have been studied.

Challenges in integration of Resonant Interband Tunnel Devices with CMOS

The fabrication of SiGe Resonant Interband Tunnel Devices (RITD) using CMOS compatible processes requires ability to form RITD structures selectively on source/drain regions. Various approaches were investigated and RITDs have been realized in lithographically defined openings in oxide on Si wafers. Patterned growth RITD on p+ Si exhibited a peak-to-valley current ratio (PVCR) of 3.0 and peak current density (J/sub p/) of 188 A/cm/sup 2/ whereas RITD on p+ implanted regions resulted in a PVCR of 2.5 with J/sub p/ of 278 A/cm/sup 2/. Blanket growth RITD on p+ implanted substrate yielded a superior PCVR of 3.3 and J/sub p/ of 332 A/cm/sup 2/. The observed effects of patterned growth and implanted substrate on the RITD device performance are critical challenges addressed in this study for RITD-CMOS integration.

High Temperature Characterization of Si/SiGe Resonant Interband Tunnel Diodes

Co-integration of Si-based tunnel diodes and CMOS circuits has been proposed for several years as a means to lower power consumption, reduce operating voltage and shrink device count. Recently, the successful integration of Si/SiGe resonant interband tunnel diodes [1,2] with CMOS [3] was demonstrated with room temperature operation. However, integrated circuits realistically operate significantly above room temperature, usually around 373K. Therefore, SPICE models used by circuit designers must account for device performance variations due to temperature changes ranging from 300K to 473K. For circuit applications, the key tunnel diode parameters are the peak and valley current densities (Jp and Jv, respectively) as well as the peak-to-valley current ratio (PVCR). Previous high temperature studies on Si-based Esaki diodes [4-6] and Si/SiGe resonant interband tunnel diodes (RITD) [7] showed some dissimilar trends for PVCR. This study examines the high temperature operation of Si/SiGe RITD more closely up to 473K. Figure 1 illustrates the schematic diagram of the various RITD structures investigated in this study. The intrinsic layer between the δ-doped planes consists of X nm of undoped Si and Y nm of undoped SiGe. Three different structures with 1nm/3nm, 2nm/4nm, and 4nm/4 nm of X/Y i-layer thicknesses, named TD-A, TD-B, and TD-C, respectively were fabricated using low temperature molecular beam epitaxy. The current-voltage characteristics of these devices were measured using a Keithley 4200 Semiconductor Parameter Analyzer. The temperature of the heat chuck was controlled via an ΩE Omega CSC32-J bench top controller. A thermocouple was mounted in direct contact with the wafer for all measurements. Initial measurements were taken at room temperature, with subsequent readings in 10K increments from 300K to 473K. Several measurements were also taken while the wafer was cooling down. Those results were consistent with the initial heat up measurements. The I-V characteristics were not found to vary significantly over a two hour time period for any particular temperature. Figure 2 shows the I-V characteristics for device TD-C. The general shape of the curve remains the same over the entire temperature range. Figure 3 overlays valley currents normalized with respect to the room temperature valley current for TD-C as well as data from other published studies [5-7]. It should be noted that the normalized Jv data for TD-A and TD-B directly overlays TD-C and Jin’s data [7]. Si/SiGe RITD valley current shows a weak temperature dependent signature. In contrast Esaki diodes formed by proximity annealing [5,6] exhibit a stronger temperature sensitivity. As illustrated in Fig. 4, the PVCR of TD-A, TD-B, and TD-C decreases as temperature increases. Device TD-A has a PVCR of 1.99 at 373 K. However, devices TD-B and TD-C resulted in PVCRs of 2.58 and 2.91 at 373 K, respectively. Overall, there was no significant effect on the device characteristics from heating the Si/SiGe RITDs. The PVCRs observed at 373 K were found to be sufficient for digital circuit/memory circuit operation. These results conclusively demonstrate that high temperature operation will not be a limiting factor in CMOS/RITD circuitry.

Analysis of the Biasing Conditions and Latching Operation for Si/SiGe Resonant Interband Tunnel Diode Based Tunneling SRAM

A memory cell utilizing negative differential resistance (NDR) characteristic of tunnel diodes was first proposed by Goto et al. in 1960 [1]. The inherently fast tunneling phenomenon and low power consumption makes this type of memory architecture attractive. Combined with the possibility for vertical integration of the tunnel diode directly atop of the source/drain region of the FET, a compact design can be achieved. The concept was further refined by Van der Wagt et al. to achieve low stand-by power by utilizing diode junction capacitance to lower peak and valley current densities. Utilizing InP/InGaAs resonant tunnel diode (RTD), a nA operation was realized [2]. The realization in Si-based system, however, is still limited. Utilizing pSi/oxynitride/npoly Si tunnel diodes, Morimoto et al. demonstrated a low voltage T-SRAM [3]. The performance was limited by the poor performance of the tunnel diode and the lack of capability to scale current density and size. In recent work by the authors, Si/SiGe resonant interband tunnel diodes (RITDs) have been successfully integrated with CMOS devices. A low voltage monostable-bistable logic element (MOBILE) latch has been demonstrated [4]. The current density of a Si/SiGe RITD is controlled by adjusting the SiGe i-layer thickness, making it suitable for circuit integration with CMOS [5]. In this work, Si/SiGe RITD-based T-SRAM cell is bread-boarded and its latching mechanisms have been investigated extensively. As shown in Fig. 1(a), each T-SRAM cell consists of two tunnel diodes connected in series with a current manipulator, NFET, connected into the sense node. In this experiment, Si/SiGe RITDs with 6 nm i-layer grown on top of p implanted wells with PVCR of 2.25 and peak current density of 2.15 kA/cm were used. During the stand-by (SB) mode, NFET is off, and VDD is fixed at 1.0V, as illustrated in Fig. 1(b). RITD1 and RITD2 function as the driver and load, respectively, resulting in folded currentvoltage characteristics as depicted in Fig. 2. The intersections the drive and load curves indicate two stable latching states, stand-by low (SBL) and high (SBH) at 246 mV and 746 mV, respectively. These two states represent logic low and high, respectively. It is important to note that the intersection at the negative differential resistance (NDR) region is unstable and is not be used as a latching point. To latch into logic high, a current has to be supplied into the sense node through the NFET by applying a bias of 2.0V to both the drain and gate. Fig. 1(c) depicts the circuit diagram during this write high (WH) cycle. By activating the NFET, a current path parallel to RITD2 is formed, elevating the overall current that passes through the load diode as shown in Fig. 3. At the same time, current injection into the middle node also causes a decrease in drive current. As a result, the potential at the sense node (VSN) changes abruptly from point A, 246 mV, to B, 802 mV. By restoring the stand-by biasing conditions, i.e. shut-off the NFET, VSN restores to the nearest stable latching state at 746 mV, point C. In the write to logic low (WL) cycle, current is subtracted or drained from the sense node by simply applying a bias to the gate of the NFET and grounding the bit node. Since there is a potential difference between sense and bit node, current will flow out of the sense node as illustrated in Fig. 1(d). In other words, a current path parallel to RITD1 is created, causing a rise in the drive current. Unlike the write high cycle, the load characteristic is undisturbed during WL cycle. As a result, VSN changes suddenly from point C, 746 mV, to D, 199 mV (Fig. 4). Restoration to the stand-by conditions shifts the latching point back to A, 246 mV. The corresponding time diagram of write and read cycles is given in Fig. 5. Slight discrepancies between the values from I-V curves and transient diagram is due to parasitic resistance present in the test setup. In conclusion, a prototype of Si/SiGe RITD-based T-SRAM has been presented. Load line analysis is performed to understand the latching mechanisms during the write and read cycles. This demonstration will lead to realization of fully-integrated Si/SiGe RITD/NMOS T-SRAM. Ultra-low power tunneling SRAM can be achieved by utilizing low current density RITDs.

Si-Based Resonant Interband Tunnel Diode/CMOS Integrated Memory Circuit

The development of Si-based tunneling-based static random access memory (TSRAM) has been described. This multi-institutional research endeavor has successfully demonstrated for the first time an integrated TSRAM that utilizes Si/SiGe resonant interband tunnel diode (RITD) and conventional NMOS. The memory cell exhibits a bistable latching operation at a low power supply voltage below 0.5 V. The key to success in the tunnel diode-based novel memory research at RIT is mutual collaboration between the institutions from the universities, government, and industry, which provides a hotbed for technological innovations and creativity.