Sean L. Rommel

''p-on-n'' Si interband tunnel diode grown by molecular beam epitaxy

Si interband tunnel diodes have been successfully fabricated by molecular beam epitaxy and room temperature peak-to-valley current ratios of 1.7 have been achieved. The diodes consist of opposing n- and p-type δ-doped injectors separated by an intrinsic Si spacer. A “p-on-n” configuration was achieved for the first time using a novel low temperature growth technique that exploits the strong surface segregation behavior of Sb, the n-type dopant, to produce sharp delta-doped profiles adjacent to the intrinsic Si spacer.

NMOS/SiGe Resonant Interband Tunneling Diode Static Random Access Memory

Tunneling-based static random access memory(SRAM)has been sought as a viable solution for a lowpower and high speed embedded memory application. The first cell design, proposed by Goto et al. [1],consists oftwotunnel diodes connected in series, oneacting as the drive andthe other as the load as showninFig. 1. This configuration allows for bistable operation at a particular range ofsupply voltages (VDD). Theinformation is stored at the sense node, whichcanbe altered by modulating current into the node via a FET.Byinjecting a current into the sense node, the cell is forced to latch to a high state as illustrated in Fig l(b).During write low operation, the FETis used to discharge the cell, pulling the sense node potential to a lowstate as depicted in Fig l(c). The demonstration ofthis type of bistable latch has been done in the Ill-Vmaterial system, showing avery promisingperformance bothin speedandpowerdissipation [2]. Morimotoetal. realizedthe systemin Si

Overgrown Si/SiGe resonant interband tunnel diodes for integration with CMOS

The incorporation of tunnel diodes with field effect transistors (FET) can improve the speed and power capability in electronic circuitry. This has been realized in III-V materials by demonstrating a low power refresh-free tunneling-SRAM and high performance compact A/D converter. A new thrust to integrate tunnel diodes with the mainstream CMOS technology led to the invention of Si/SiGe resonant interband tunnel diode (RITD) (S.L. Rommel et al., Appl. Phys. Lett., vol. 73, pp. 2191-93, 1998) with the highest reported peak-to-valley current ratio (PVCR) of 6.0 (K. Eberl, J. Crystal Growth, 227-228, pp. 770-76, 2001). The structure consists of a SiGe spacer i-layer sandwiched between two delta-doped planes grown by low-thermal molecular beam epitaxy (LT-MBE) (N. Jin et al., IEEE Trans. Elec. Dev., vol. 50, pp. 1876-1884, 2003). By adjusting the spacer layer thickness, the peak current density (Jp) can be adjusted from 0.1 A/cm/sup 2/ up to 151 kA/cm/sup 2/ (N. Jin et al., App. Phys. Lett., 83, pp. 3308-3310, 2003). Recently, monolithic integration of RITD with CMOS has been realized, demonstrating a low-voltage operation of a monostable-bistable logic element (MOBILE) (S.Sudirgo et al., Proc. 2003 Int. Semic. Dev. Res. Symp., pp. 22, 2003). In this study, RITD layers were grown through openings in a 300 nm thick chemical vapor deposition (CVD) SiO/sub 2/ layer.

High Temperature Characterization of Si/SiGe Resonant Interband Tunnel Diodes

Co-integration of Si-based tunnel diodes and CMOS circuits has been proposed for several years as a means to lower power consumption, reduce operating voltage and shrink device count. Recently, the successful integration of Si/SiGe resonant interband tunnel diodes [1,2] with CMOS [3] was demonstrated with room temperature operation. However, integrated circuits realistically operate significantly above room temperature, usually around 373K. Therefore, SPICE models used by circuit designers must account for device performance variations due to temperature changes ranging from 300K to 473K. For circuit applications, the key tunnel diode parameters are the peak and valley current densities (Jp and Jv, respectively) as well as the peak-to-valley current ratio (PVCR). Previous high temperature studies on Si-based Esaki diodes [4-6] and Si/SiGe resonant interband tunnel diodes (RITD) [7] showed some dissimilar trends for PVCR. This study examines the high temperature operation of Si/SiGe RITD more closely up to 473K. Figure 1 illustrates the schematic diagram of the various RITD structures investigated in this study. The intrinsic layer between the δ-doped planes consists of X nm of undoped Si and Y nm of undoped SiGe. Three different structures with 1nm/3nm, 2nm/4nm, and 4nm/4 nm of X/Y i-layer thicknesses, named TD-A, TD-B, and TD-C, respectively were fabricated using low temperature molecular beam epitaxy. The current-voltage characteristics of these devices were measured using a Keithley 4200 Semiconductor Parameter Analyzer. The temperature of the heat chuck was controlled via an ΩE Omega CSC32-J bench top controller. A thermocouple was mounted in direct contact with the wafer for all measurements. Initial measurements were taken at room temperature, with subsequent readings in 10K increments from 300K to 473K. Several measurements were also taken while the wafer was cooling down. Those results were consistent with the initial heat up measurements. The I-V characteristics were not found to vary significantly over a two hour time period for any particular temperature. Figure 2 shows the I-V characteristics for device TD-C. The general shape of the curve remains the same over the entire temperature range. Figure 3 overlays valley currents normalized with respect to the room temperature valley current for TD-C as well as data from other published studies [5-7]. It should be noted that the normalized Jv data for TD-A and TD-B directly overlays TD-C and Jin’s data [7]. Si/SiGe RITD valley current shows a weak temperature dependent signature. In contrast Esaki diodes formed by proximity annealing [5,6] exhibit a stronger temperature sensitivity. As illustrated in Fig. 4, the PVCR of TD-A, TD-B, and TD-C decreases as temperature increases. Device TD-A has a PVCR of 1.99 at 373 K. However, devices TD-B and TD-C resulted in PVCRs of 2.58 and 2.91 at 373 K, respectively. Overall, there was no significant effect on the device characteristics from heating the Si/SiGe RITDs. The PVCRs observed at 373 K were found to be sufficient for digital circuit/memory circuit operation. These results conclusively demonstrate that high temperature operation will not be a limiting factor in CMOS/RITD circuitry.

Monolithic vertical integration of Si/SiGe HBT and Si-based resonant interband tunneling diode demonstrating latching operation and adjustable peak-to-valley current ratios

We report the first monolithic vertical integration of a Si/SiGe HBT with a Si-based resonant interband tunnel diode (RITD) on a silicon substrate. This enables a 3-terminal negative differential resistance (NDR) device and the resulting devices have the distinguishing characteristics of adjustable peak-to-valley current ratio and adjustable peak current density (PCD) in the collector current under common emitter configuration at room temperature. We experimentally demonstrate its latching property and switching operation based on quantum mechanics.

Temperature dependent empirical modeling of proximity diffused Si esaki diodes and memory circuits

In this paper, the modified Sze model developed by the authors fits the measured IV characteristics very well for both forward and reverse biases at temperatures ranging from 23degC up to 200degC. Simulations of a TSRAM timing diagrams at multiple temperatures show the viability of using the developed model for accurate simulation and characterization of tunnel diode augmented CMOS circuits, including temperature effects.