D. Renshaw

Alpha channel estimation in high resolution images and image sequences

For motion picture special effects, it is often necessary to take a source image of an actor, segment the actor from the unwanted background, and then composite over a new background. The standard approach requires the unwanted background to be a blue screen. While this technique is capable of handling areas where the foreground blends into the background, the physical requirements present many practical problems. This paper presents an algorithm that requires minimal human interaction to segment motion picture resolution images and image sequences. We show that it can be used not only to segment badly lit or noisy blue screen images, but also to segment actors where the background is more varied.

Spike timing dependent plasticity (STDP) can ameliorate process variations in neuromorphic VLSI

A transient-detecting very large scale integration (VLSI) pixel is described, suitable for use in a visual-processing, depth-recovery algorithm based upon spike timing. A small array of pixels is coupled to an adaptive system, based upon spike timing dependent plasticity (STDP), that aims to reduce the effect of VLSI process variations on the algorithms performance. Results from 0.35 /spl mu/m CMOS temporal differentiating pixels and STDP circuits show that the system is capable of adapting to substantially reduce the effects of process variations without interrupting the algorithms natural processes. The concept is generic to all spike timing driven processing algorithms in a VLSI.

Race-free clocking of CMOS pipelines using a single global clock

To ease global clock distribution in a synchronous system extending over several levels of interconnect (for example between logic blocks within a chip, chips mounted on a printed circuit board and boards of chips across a backplane), a race-free clocking scheme for CMOS VLSI requiring a single clock line is presented. Since the technique is race-free, the clock line may be driven by a sinusoid, thereby avoiding the transmission of the higher frequency components associated with fast clock edges. In this way, clock signal distortion due to transmission line effects will be kept to a minimum.

Performance of reference block updating techniques when tracking with the block matching algorithm

An important problem when using the block matching algorithm to track objects is how to update the reference block to take account of the changing target appearance. This paper investigates and reports on the accuracy and stability of a variety of update strategies and on the robustness of these strategies to image noise. These strategies are applicable where an object is being tracked using the block matching algorithm over an extended period of time or where the object appearance is changing over time.

Intelligent CMOS imaging

We report on the integration of computational and control functions with image sensor arrays using commodity CMOS processes. The sensors are highly efficient, high density arrays of photo-diodes, with a minimal overhead of one transistor per pixel. We report production arrays of up to 786 X 576 pixels of 10.5 micrometers pitch in 0.8 micrometers double metal single poly CMOS. We also report techniques presently in development to achieve 7.5 micrometers pitch in the same technology. These sensors are fully self-contained with regard to drive and sense electronics. Typical off-chip needs are limited to a clock crystal, supply regulator and some decoupling capacitors. `Intelligence is provided in the form of analogue and digital functions integrated on the same chip as the sensors. Such functions can include 8- bit ADC, on-chip exposure control and computational functions to achieve color restoration. Integration of these parts allows us to construct a single chip color camera. Results from a proto-type color CMOS camera system are given. Successful realization of these functions leads to order of magnitude reductions in system cost, size and power-consumption when compared to the CCD alternative.

Case studies in VLSI signal processing using a silicon compiler

We advocate a custom approach to VLSI signal processing using a Silicon Compiler. Through the Compiler. system designers with no previous VLSI experience may enjoy all the advantages of an integrated system implementation. At the same time, cost and timescales are dramatically lower than those conventionally associated with custom design. To illustrate these advantages we present case studies of some VLSI systems currently in development at Edinburgh.

A bit serial linear array DFT

A Linear array which computes the DFT in a pipelined fashion is described. The algorithm is derived from the batch processing array proposed by H.T. Kung [1] but has been modified to allow continuous operation. This computation of the DFT is a complex polynomial evaluation on the unit circle using Horners method having the data for the polynomial coefficients. Data and the N-th complex roots of unity are input at one end of the array and the DFT sequence is output from the other. The polynomial coefficients are stored in successive modules in the array and a new batch is latched successively with a synchronising signal. In its simplest form the design has a single system part which is replicated N times for an N-point transform. For time multiplexed modules the system throughput and hardware can be optimised for given applications. A bit serial layout for 6 micron NMOS VLSI has been designed and simulated using the FIRST silicon compiler at the University of Edinburgh.

Minimizing risk using prediction uncertainty in neural network estimation fusion and its application to papermaking

The paper presents Bayesian information fusion theory in the context of neural-network model combination. It shows how confidence measures can be combined with individual model estimates to minimize risk through the fusion process. The theory is illustrated through application to the real task of quality prediction in the papermaking industry. Prediction uncertainty estimates are calculated using approximate Bayesian learning. These are incorporated into model combination as confidence measures. Cost functions in the fusion center are used to control the influence of the confidence measures and improve the performance of the resultant committee.

A Comparison of Vector Quantization Codebook Generation Algorithms Applied to Automatic Face Recognition

Automatic facial recognition is an attractive solution to the problem of computerised personal identification. In order to facilitate a cost effective solution, high levels of data reduction are required when storing the facial information. Vector Quantization has previously been used as a data reduction technique for the encoding of facial images.

Design and realisation of adaptive lattice filters

This paper compares the relative advantages of discrete and integrated circuit transversal and lattice adaptive filter designs. It discusses the trade-offs between the traditional transversal filter and the gradient adaptive lattice (GAL), showing that the reliable rate of convergence of the lattice is offset by a greater complexity and algorithm noise. Two 16-stage hardware implementations are described. One is a TTL GAL equaliser based on a single 12-bit parallel multiplier. The second is a suite of 5 custom NMOS bit-serial arithmetic LSI chips, which together make a lattice prediction-error filter. Both implementations offer 12-bit precisions and bandwidths of over 8 kHz. This shows that the increased complexity of the lattice approach can easily be accommodated in custom VLSI circuit designs.