Peter B. Denyer

Serial-data computation

1: Introduction.- The case for serial-data techniques.- The case against serial-data techniques.- Historical overview of bit-serial techniques.- Final comments.- 2: The First Generation.- FIRST.- The FIRST primitive set.- Bit-serial systems design.- Case study.- FFT subsystem design.- Filterbank subsystem design.- System specifications.- Initial design issues and decisions.- Functional design - the soft model.- Physical design - the hard model.- Test strategy and confidence levels.- A critical appraisal of FIRST.- 3: Rudiments.- Issues of space and time.- Control.- Twos complement integer coding.- Fundamental building blocks - the atoms.- Numerical principles of serial-data additive operations.- Partitioning issues.- 4: Twos Complement Multiplication.- Derivation from bit-parallel architectures.- Scrutiny of two serial-data multipliers.- Word-level equivalent architectures.- Comparison of the S/P and Lyon multipliers.- Serial/parallel multiplier environments.- Other approaches.- 5: Area-Saving Techniques.- Overview of vector computation.- Symmetric-coded serial/parallel muiltiplier.- Serial/parallel inner-product computer.- Architectural case studies.- Architectural synthesis.- Distributed arithmetic in context.- Cascading DA modules.- Incremental computation of squares/sums of squares.- Final comments.- 6: Throughput Enhancement.- Twin-pipe.- Radix-4.- Multi-precision.- Interfacing between operational domains.- The automultiplier.- Final comments.- 7: The Second Generation.- Process-independence.- Overview of SECOND.- PRIMITIVE specification (design capture).- PRIMITIVE verification (behavioural simulation).- Semi-custom PRIMITIVE implementation.- Custom PRIMITIVE implementation.- Other approaches.- Final comments.- 8: Concluding Remarks.- References.- Appendix A - Complex Multiplier.- Appendix B - Logic Synthesis.

ASIC image sensors

Two image array sensors designed and fabricated using a standard two-level metal ASIC CMOS process are described. The results show that good quality grey-level images can be formed, and that CMOS sensors arrays can be successfully integrated with efficient analogue sense amplifiers and with digital control/image-processing logic. The first sensor is a prototype 128*128 pixel test array. The second is a 312*287 pixel image sensor chip which includes all the necessary circuitry to produce full PAL format video output, as well as automatic electronic exposure control and built-in test circuits. Test results characterizing the devices are given, covering dynamic range, spectral response, sensitivity, resistance to blooming, etc. Some potential applications for such devices are mentioned.<<ETX>>

Miniature programmable transversal filter using CCD/MOS technology

This paper describes the operational features and performance of an integrated-circuit programmable sampled-analog data filter in transversal form using CCD/MOST technology. Reasons behind the particular choice of filter architecture for a prototype realization and its comparison with other reported designs in this technology are discussed, with particular emphasis placed on a novel MOST multiplier array implementation. The performance characteristics of a prototype 64-point filter design based on this approach is detailed in the context of frequency- and matched-filtering, and a module of 256 points using four cascaded filters is also described. Techniques for optimizing the inherent performance limits of these filter types under microprocessor control are suggested, via the iterative adaption of the filter impulse response, and results are given to show the improvement obtained. Finally, the potential of this miniature integrated-circuit filter for sonar type applications is briefly discussed.

CMOS video cameras

A single chip CMOS video camera is presented, along with design technique and characterization results. The chip comprises a 312*287 pixel photodiode array together with all the necessary sensing, addressing and amplifying circuitry, as well as a 1000 gate logic processor, which implements synchronization timing to deliver a fully-formatted composite video signal and a further 1000 gate logic processor, which implements automatic exposure control over a wide range. There are also simple solutions for gamma correction and test.<<ETX>>

Synthesis of address generators

An approach is described for addressing generation hardware synthesis. The authors present algorithms and tools that describe the hardware between a binary counter and the address port of a block of memory, which is accessed in some repetitive pattern. These tools match results produced manually for examples taken from a VLSI image processing application.<<ETX>>

Address generation for array access based on modulus m counters

The necessary task of address generation for RAM and ROM accesses can often result in hardware taking up an appreciable fraction of the area of a data processing IC. Close examination of the address sequences can reveal symmetry which may be exploited to automatically devise small and simple address generators, based on counters. The authors describe automated techniques used to recognise and develop symmetries in address sequences, and to synthesise the necessary address generation hardware.<<ETX>>

The First Generation

Serial-data computational techniques have exciting implementation potential in the light of recent advances in technology for the fabrication of VLSI integrated circuits. There now exists the possibility to realise complex real-time computational algorithms which were previously of only theoretical interest [50]. Many of these algorithms are suitable for execution by dedicated pipelines of serial-data processors in compact VLSI architectures. However with the integration of hundreds of thousands of devices on a single silicon surface arises the considerable likelihood of implementation errors — a ‘complexity crisis’ confronts VLSI designers [113]. To combat complexity, structured design styles and software tools [63, 109] have emerged, culminating in the structural silicon compiler [10, 50]. Structural silicon compilers guarantee working parts from high-level structural descriptions, through automatic assembly of known-good modules by known-good techniques. Low-level design errors are avoided by forcing the designer to follow this route.

Efficient bit-serial complex multiplication and sum-of-products computation using distributed arithmetic

A bit-serial complex multiplier primitive is described, which uses distributed arithmetic to achieve significant computational savings over more conventional designs which decompose the complex multiply function into real multiply and add functions. Hardware is in the form of a modular, pipelined, cascadable linear array. Modularity ensures compatibility with automatic assembly procedures, which with its inherent testability properties makes the complex multiplier primitive an ideal addition to a cell library for silicon compilation. Component modules are identified and described, and estimates are made as to overall transistor count in static CMOS technology. Finally it is shown how a similar, reduced architecture may be used to compute more general sums of products.

Techniques to increase the computational throughput of bit-serial architectures

Three architectural techniques are reported, which accelerate bit-serial computation without compromising its favourable advantages. In essence these techniques rely on multi-wire representations of serial data - a step towards bit-parallelism. Interfacing techniques are developed to support the existence of domains of different throughput within a system, thereby enhancing the range of bandwidth-matching techniques available to the systems designer. These techniques also realise the potential to mix processing wordlengths within a serial-data system.

A single-chip CMOS 306/spl times/244-pixel NTSC video camera and a descendant coprocessor device

We report a single-chip CMOS NTSC video camera, incorporating a 306/spl times/244 image sensor array, sensor readout logic, A/D and D/A converters, and a custom 300-MIPS processor for color reconstruction and NTSC encoding. Operation is from a single 5-V supply and a 14.32-MHz crystal clock. Implementation is in 0.8-/spl mu/ single-poly-double-metal (SPDM) CMOS, integrating some 580 000 devices on a 68-mm/sup 2/ die. A related dual-standard PAL/NTSC coprocessor is also described, extending the architectural basis of the single-chip device whilst incorporating more complex signal-processing function. In this case, implementation is in 0.6-/spl mu/m SPDM CMOS, integrating some 285000 devices on a 27-mm/sup 2/ die.