Dae Hwan Hwang

A FPGA based real-time post-processing architecture for active stereo vision

This paper presents a post-processing architecture for high quality depth map in active stereo vision. The proposed architecture consists of five sub-blocks in cascade manner, which are consistency check, hole filling, variance check, weighted median filter, and joint bilateral filter. The novel design which is implemented on a single FPGA achieves 60 frames per second for 1280×720 stereo images with 256 disparity range.

Post-processing algorithms for real-time active stereo vision

This paper presents post-processing algorithms which work on a commercial FPGA for high quality stereo vision results. Specially, in this paper we focus the description of algorithms and their performance evaluation results instead of explaining hardware architecture. The proposed algorithms consists of five sub-blocks in cascade manner, which are consistency check, hole filling, variance check, weighted median filter, and joint bilateral filter. The experimental results show that error rates are 6.02% (6.57% with no using) for real world camera input(1280×720 intensity, maximum disparity 256), and 8.30% (13.7% with no using) for Middlebury stereo image set when we use the proposed post-processing.