Jae Il Cho
Electronics and Telecommunications Research Institute
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Jae Il Cho.
Applied Mathematics and Computation | 2008
Dongil Han; Byoungmoo Lee; Jae Il Cho; Dae-Hwan Hwang
This paper presents algorithms for the real-time object segmentation of the noisy disparity map obtained by stereo matching algorithm and its verification test using hardware architectures. The disparity map contains lots of noise from various causes, and it has to be refined by some noise filtering methods to make it useful for the object segmentation. Therefore refinement process is a necessary process prior to segmentation process. In our approach, refinement method based on noise removal technique is adopted for improvement of the disparity map quality. And the projection-based region merging method is used for object segmentation. The proposed algorithms are implemented in FPGA board. Results of the test show that our approach works precisely and its performance fits in conditions of real-time application. The developed real-time object segmentation system could be useful for various applications such as face recognition, object tracking, and other applications with the support of proper embedded software.
Computers & Electrical Engineering | 2012
Dongil Han; Jongho Choi; Byungwhan Kim; Jae Il Cho
This paper proposes a novel hardware structure and field-programmable gate array (FPGA) implementation method for real-time detection of multiple human faces with robustness against illumination variations. These are designed to greatly improve face detection in various environments with using MCT techniques and the AdaBoost learning algorithm which is robust against variable illumination. We have designed, implemented, and verified the hardware architecture of the face detection engine for high-performance face detection and real-time processing. The face detection chip is developed by verifying and implementing it using a FPGA and an application-specific integrated circuit (ASIC). To verify and implement the chip, we used a Virtex5 LX330 FPGA board and a 0.18@mm 1-poly and 6-metal CMOS logic process. Performance results of the implementation and verification showed it is possible to detect at least 32 faces of a wide variety of sizes at a maximum speed of 147 frames per second.
Archive | 2013
Seung Min Choi; Dae Hwan Hwang; Eul Gyoon Lim; Hochul Shin; Jae-Chan Jeong; Jae Il Cho; Kwang Ho Yang; Jiho Chang
Archive | 2010
Jae Il Cho; Seung Min Choi; Jiho Chang; Dae Hwan Hwang; Dongil Han; Hyeonjong Jo; Jongho Choi; Jaekwang Song
Etri Journal | 2015
Seung-min Choi; Jae-chan Jeong; Jiho Chang; H. J. Shin; Eul-Gyoon Lim; Jae Il Cho; Daehwan Hwang
Archive | 2010
Seung Min Choi; Jiho Chang; Jae Il Cho; Dae Hwan Hwang
Archive | 2016
Ji Ho Chang; Jae Chan Jeong; Ho Chul Shin; Dae Hwan Hwang; Seung Min Choi; Eul Gyoon Lim; Jae Il Cho; Kuk Jin Yoon
Archive | 2013
Seung Min Choi; Jae Il Cho; Dae Hwan Hwang
Archive | 2012
Ji Ho Chang; Dae Hwan Hwang; Jae Il Cho; Dongil Han; Jong Ho Choi
Archive | 2015
Ji Ho Chang; Dae Hwan Hwang; Kwang Ho Yang; Eul Gyoon Lim; Jae Il Cho