Moon-Hyun Yoo

A Unified Statistical Model for Inter-Die and Intra-Die Process Variation

An efficient characterization technique with the spatial correlation matrix from electrical device parameters such as threshold voltage and saturation current accounting for inter- and intra-die variations is demonstrated. Then, a unified statistical model based on the correlation matrix is developed and implemented to the SPICE simulator to predict the distribution of circuit performance. In order to verify our model, test chips which consist of transistors and ring oscillators were fabricated using a 130nm CMOS technology. Simulated delay/skew variations of ring oscillators agree well with the measurement of test chips, maintaining a reasonable accuracy of 85 %. Especially, we show that as the distance of the two ring oscillators becomes larger, the timing skew between them becomes bigger. Moreover, the sensitivity analysis for the performance of simple analog and digital circuit, is performed in terms of inter-and intra-die variation.

An efficient rule-based OPC approach using a DRC tool for 0.18 /spl mu/m ASIC

The increasing complexity and data volume of VLSI designs demand an efficient optical proximity correction (OPC) technique. In this paper, we address the issues related to the gate bridge, which is serious in sub-quarter micron technology, and the wide range of contact CD (Critical Dimension) variation. We present the efficient gate CD control method by introducing the critical area correction. In addition, the contact CD variation is reduced under the target CD range due to the combination of the contact biasing and the process calibration. The correction time and output data volume are drastically reduced by the hierarchical data manipulation using a DRC (Design Rule Check) tool, which basically exploits the characteristics of the design layers in ASICs. The newly proposed incremental on-line violation filtering method also reduces the correction cycle time significantly.

A fast lithography verification framework for litho-friendly layout design

The increase in pattern complexity due to optical proximity correction (OPC), the tight requirements for critical dimension (CD) control and the difficulties in defect inspections make IC manufacture more expensive. To alleviate the high cost, manufacturing requirements must be handled at the design stage to improve the quality and yield of ICs. We demonstrate the extraction of critical areas for detecting failures and a new lithography simulation method for full-chip level optical proximity corrected layout. The methodology has been used in our mask verification process that is called litho-friendly layout (LFL). For the critical area extraction, we present three approaches using process window, normalized image log-slope (NILS) and edge placement error (EPE). For full-chip level simulation, we introduce an automatic calibration method for simulation process parameters, a mask decomposition method and a selective simulation method. The verification process includes lithography process simulation, print-image based LVS (layout vs. schematic) and DRC (design rule check). We also demonstrate that LFL can provide guidelines for better OPC of sub-80 nm processes.

MEEF-based correction to achieve OPC convergence of low-k1 lithography with strong OAI

The quality of model-based OPC (MBOPC) depends on both modeling and correction accuracy. As the k1 process factor decreases and design complexity increases, the correction accuracy becomes more important. Especially, in case of high NA immersion lithography with strong off-axis illumination (OAI) such as dipole and cross-pole illumination, mask error enhancement factor (MEEF) and normalized intensity log-slope (NILS) vary seriously according to the pattern directions and shapes, so that the normal correction method, which uses the constant damping value, causes the divergence of correction and can hardly define optimum bias. Therefore, we developed design rule (D/R) constraints and new correction method to prevent the divergence and to reduce the OPC run time for sub-60nm device. In this paper, D/R constraints derived from MEEF are introduced to reduce MEEF across the full chip. In addition, we propose new methods to achieve the global OPC convergence of low-k1 lithography by MEEF-based correction combined with proportion-integral-derivative (PID) controller. The PID controller can prevent the divergence because it considers the derivative term between EPEs (edge placement error) of previous and current iteration. Since MEEF-based correction uses the variable damping value derived from MEEF of each pattern fragment, it is effective for the convergence of the memory bit-line layer composed of the complicated 2D patterns. MEEF-based correction combined with PID controller merges the merits of each method and is found to be a stable correction method for k1 factor smaller than 0.27. Applying the proposed method, we could remove the process weak points having more than 20% CD variation caused by the divergence and achieve sufficient process margin for sub-60nm memory device. OPC run time is also reduced by 40% compared with the normal correction method.

65.4: Improvement in Luminous Efficacy of Ultra‐Fine Discharge Cells for 50‐in. Full‐HD Plasma TV

In order to develop ultra-fine discharge cells with high luminous efficacy, several efforts have been made. We designed cell structures for the image element pitch of 0.58 mm. Both HEXA and MARI structures were considered. As for luminous efficacy, in constructing a 50-inch full HD PDP, we set a challenging goal to 2.0 lm/W. We believe high speed sustaining in high Xe content can help, because this is not restricted to small cell area. In addition, we developed ultra fine barrier fabrication method using sandblasting with 30 μm in width. This may contribute to improve efficacy further by enlarging discharge space.

New OPC methods to increase process margin for sub-70nm devices

Current model-based OPC methods are targeting the critical dimension and the fidelity of the design layout. These methods cannot suitably consider the process margin and reveal several problems below 70nm design layout with the low k1 process factor. Although litho-friendly layout methods have been introduced to improve the photolithography process margin, designing perfect litho-friendly layout is difficult because of the designer’s lacking of knowledge about the process and the relationship between the layers. Thus we have developed new OPC methods to increase the process margin for sub-70nm process. In this paper we propose new methods to generate the OPC-friendly layout from the original design by 1) rule-based retargeting, 2) model-based retargeting using NILS values, and 3) model-based retargeting by MEEF values. In addition, we have evaluated the post-processing treatment by NILS or MEEF values after the model-based OPC. The proposed OPC methods are effective for the memory bit line layer and metal layers, which are composed of the complicated 2-dimensional configuration and also have the advantage to compensate the model inaccuracy for the layout having non-periodic pattern structure. While the rule-based retargeting method requires high engineering cost to optimize the retargeting rule, the model-based retargeting method can be easily implemented into the conventional OPC process and do not need the extraction process of the retargeting rule which is not simple for the 2-dimensional patterns. Applying the model-based retargeting we could increase the DOF margin by 50% compared to the normal OPC method for sub-70nm memory device with ArF lithography. It is more effective to use these retargeting methods from the defocused OPC models.

Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis

As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We propose a method to determine whether aggressors can potentially switch simultaneously with the victim or not. The functional information is used to classify the aggressors. Our functional pruning algorithm inspects the conflict of the net states using CNF (conjunction normal form) and BDD (binary decision diagram). We present the experimental results on several industrial circuits. In the experiments, 6.4% of total aggressors are false and the accuracy of delay calculation can be improved up to 36.6%.

Statistical retention modeling in floating-gate cell: ONO scaling

The simulation study of the ONO gate stack scaling, which includes the Monte-Carlo statistical analysis of time-dependent Vth distribution and SILC is performed. Leakage through both tunneling and blocking oxide is taken into account including multi-trap tunneling paths. Exact 50nm floating-gate cell structure is used instead of simple 1D stack for modeling and comparison with experimental data. Analysis of the influence of trap parameters on scaling trends is given.

Analysis for complex power distribution networks considering densely populated vias

Due to the high speed and low power trends, the power distribution network (PDN) in multilayer printed circuit boards (PCBs) plays a pivotal role in terms of system performance. The paper presents an efficient analysis method for the irregularly shaped power/ground plane pair considering the effect of densely populated power/ground and signal vias in the frequency domain. The plane is divided based on geometric properties and modeled by the parallel-plate transmission line theory. For examination of various via effects, we have modeled vias according to their properties, such as power, ground and signal. Using a conventional circuit simulator, the input- and trans-impedance of power/ground planes are investigated. Since the proposed method is accurate as well as fast, it can be efficiently applied to multilayered PCB structures at the early design stage.

Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination

The k1 factor of the 65nm node device approaches to around 0.3 or even below because the device shrinking is much faster than the development speed of the high NA ArF scanner. Since the conventional model-based OPC (MBOPC) is only focused on patterning of the layout on the wafer as exactly same as the original design, it can hardly guarantee enough process margin in the low-k1 lithography regime. In this paper, illumination shape and retargeting rule of the multi-step OPC are optimized to improve the process margin of the 65nm node memory device. Sigma width and open angle of the dipole illumination is optimized to resolve the minimum pitch and to maintain the critical dimension (CD) uniformity. Even though the illumination is optimized and litho-friendly layout (LFL) [1] is applied, there is the process weak point caused by the device architecture. Applying the full-chip level verification, it is found that most of process weak points exist in isolated and semi-dense patterns of the core and peripheral region. The full-chip level verification uses the vector thin film model for the accurate resist image simulation of the high NA scanner. As the mask error enhancement factor (MEEF) is getting larger in the 65nm node device, the mask mean to target (MTT) rises as the dominant factor of the process margin. The NILS according to mask MTT variation is adopted as criterion for the process weak point extraction. Since the NILS of process weak point can be improved by the increasing pattern with, retargeting rules such as selective bias and pattern shift are applied. Under the dipole illumination, the NILS distributions of parallel and perpendicular patterns are different and the different retargeting rules are applied to them. Applying proposed illumination and multi-step OPC optimization to the 65nm node memory device, we have validated that our methodology can insure enough process margin for the volume production.