Jong-bae Lee

A Unified Statistical Model for Inter-Die and Intra-Die Process Variation

An efficient characterization technique with the spatial correlation matrix from electrical device parameters such as threshold voltage and saturation current accounting for inter- and intra-die variations is demonstrated. Then, a unified statistical model based on the correlation matrix is developed and implemented to the SPICE simulator to predict the distribution of circuit performance. In order to verify our model, test chips which consist of transistors and ring oscillators were fabricated using a 130nm CMOS technology. Simulated delay/skew variations of ring oscillators agree well with the measurement of test chips, maintaining a reasonable accuracy of 85 %. Especially, we show that as the distance of the two ring oscillators becomes larger, the timing skew between them becomes bigger. Moreover, the sensitivity analysis for the performance of simple analog and digital circuit, is performed in terms of inter-and intra-die variation.

Magnetic and Electrical Properties of Magnetic Tunnel Junctions With Radical Oxidized MgO Barriers

This work focuses on magnetic tunnel junctions with a MgO barrier layer made by RF-sputtering and radical oxidation. In case of RF-sputtered MgO, its crystal orientation, MR and RA values very sensitively depend on the chamber atmosphere. The MR ratio of 97% in radical oxidized MgO is obtained at 0.4 V, which is slightly higher than RF-sputtered MgO. Also, its RA is smaller than that of RF-sputtered MgO. These improved MgO properties are originated from the improvement of the crystal orientation of MgO(200) and the decrease of OH component within the MgO barrier. In addition, the breakdown voltage in radical oxidized MgO is higher than that of RF-sputtered MgO at the same MgO thickness

An indirect extraction of interconnect technology parameters for efficient statistical interconnect modeling and its applications

In this paper, we present the new extraction environment of interconnect technology parameters (ITP). The indirect and automatic extraction methodology, which is applicable to arbitrary test patterns and measurement data, is implemented into this environment. Statistical variations of ITP in 0.25 /spl mu/m technology are characterized in a fully indirect way. The estimated 3-/spl sigma/ variation of the IMD thickness is more than 20%, which demonstrates the importance of the statistical interconnect modeling in deep sub-micron technology. The extraction environment is also applied to the modeling of the multi-layer conformal dielectric and results are discussed. Interfacing the statistical interconnect modeling to the full-chip RC extraction is briefly discussed.

SilcVerify: An Efficient Substrate Coupling Noise Simulation Tool for High-Speed & Nano-Scaled Memory Design

In this paper, the authors propose a switch-level substrate noise simulation tool named SilcVerify for high-speed memory design based on lightly-doped and nanoscaled CMOS processes. It uses the device switching model (DSM) as its noise source and the adjacent geometry dependent macromodel (AGDM) as its substrate model. The DSM represents the noise injection of each transistor into the substrate. It consists of one current source and one capacitance. The AGDM is a scalable model based on the layout geometry and Voronoi tessellation. Consequently, a sparse network composed with DSMs and AGDMs is solved by using a linear system solution technique. Experimental results for real designs verify that SilcVerify can simulate three orders larger circuits and two orders faster than the reference method using a 3D substrate model and a nonlinear circuit simulator while maintaining the accuracy of about 10% error. SilcVerify can be applied to block placement and guard-ring optimization for PLL jitter reduction

Statistical leakage estimation for DRAM circuits

Power consumption has become a key constraint in VLSI designs. Leakage current becomes a dominant part of the total power dissipation. In addition, with technology scaling into sub-50nm regime, one of the main design challenges in the presence of process variations is to cope with the uncertainties in timing and power. Since the leakage current is highly dominated by process variations, the statistical leakage estimation is essential for robust circuit design. Process variations can be monitored by analyzing the test element group (TEG). DRAM has power down mode with ICC2P parameter. To obtain ICC2P current, we need a long circuit-level simulation with an accurate transistor modeling. Therefore, to solve this problem, we need a practical framework which is based on switch-level and standby vector dependent statistical leakage analysis. In this paper, we proposed a TEG based analysis methodology to estimate the leakage current at ICC2P mode. Experiments on DRAM benchmark circuits demonstrate that the estimated results with our methodology are very accurate compared to the measurement data from industrial fabrication.

Retardation of the onset time for signal dropout arising from wear debris using diamond-like carbon overcoats on the VCR head

An investigation was conducted to examine the effects of diamond-like carbon (DLC) overcoats on the wear durability of the VCR head and the signal dropout caused by wear debris while the VCR is in operation. Approximately 40-nm-thick DLC films were deposited directly on the Mn-Zn ferrite head pole by an electron cyclotron resonance (ECR) system using CH/sub 4/ source gas. The deposition temperature was maintained at below 100/spl deg/C to prevent deterioration of the epoxy resin attached to the head. From the experiment we were able to discover that DLC films accumulated successively from the bottom of the grooves on the head surface smoothing out the surface. In general, DLC heads outperformed the bare heads. The head life is increased significantly by the wear durability of DLC films and the continuous supply of lubricating DLC films. We were also able to discover that leftover DLC films along the head edge provide continuous lubricity on the rubbing head surface during use. Furthermore, most of the wear debris was more readily expelled from the DLC head surface than from the bare head. Therefore, the onset time of the signal dropouts was found to be delayed six times in DLC heads in the still frame mode.

Fast layout processing methodologies for scalable distributed computing applications

As the feature size shrinks to sub-20nm, more advanced OPC technologies such as ILT and the new lithographic resolution by EUV become the key solutions for device fabrication. These technologies leads to the file size explosion of up to hundreds of gigabytes of GDSII and OASIS files mainly due to the addition of complicated scattering bars and flattening of the design to compensate for long range effects. Splitting and merging layout files have been done sequentially in typical distributed computing layout applications. This portion becomes the bottle neck, causing the scalability to become poor. According to the Amdahls law, minimizing the portion of sequential part is the key to get the maximum speed up. In this paper, we present scalable layout dividing and merging methodologies: Skeleton file based querying and direct OASIS file merging. These methods not only use a very minimum memory footprint but also achieve remarkable speed improvement. The skeleton file concept is very novel for a distributed application requiring geometrical processing, as it allows almost pseudo-random access into the input GDSII or OASIS file. Client machines can make use of the random access and perform fast query operations. The skeleton concept also works very well for flat input layouts, which is often the case of post-OPC data. Also, our OASIS file merging scheme is a smart approach which is equivalent of a binary file concatenation scheme. The merging method for OASIS files concatenates shape information in binary format with basic interpretation of bits with very low memory usage. We have observed that the skeleton file concept achieved 13.5 times speed improvement and used only 3.78% of memory on the master, over the conventional concept of converting into an internal format. Also, the merging speed is very fast, 28MB/sec and it is 44.5 times faster than conventional method. On top of the fast merging speed, it is very scalable since the merging time grows in linear fashion with respect to the file size. Our experiment setup includes hundreds of gigabytes of GDSII and OASIS files. We demonstrate in the paper, that the skeleton file based querying and direct OASIS file-merging schemes are very scalable for distributed computing applications for large volume layout. Additionally, we used embedded skeleton file scheme to improve file loading speed in layout viewer system and achieved 61 time speedup. We used Nirmaan, SoftJins post-layout EDA toolkit for skeleton file based querying, OASIS file-merging and embedded skeleton file schemes.

Fast power delivery network analyzer

With the increase in circuit frequency and supply voltage Scaling, a robust power network design is essential to ensure that the circuits on a chip operate reliably at the guaranteed level of performance. Traditionally the power network analysis has its main focus on IR-drop effects. However, IR drop analysis approaches have strong dependence on the input vectors and may require a tremendously long execution time. In this paper, we propose a novel and fast power network analysis method which calculates the effective resistance between all power pads and power grids. This method explores huge parasitic power networks and detects hot spots with an abnormal effective resistance value resulted from gross errors in the post-layout power network. We currently use the proposed method for our memory and DDI circuits to validate the post-layout power network quickly. We developed our method by using multi-thread and multi-process techniques, resulting in up to 50 times speed improvement.

A novel pattern error detecting algorithm for SEM images of mask monitoring patterns

In mask fabrication, e-beam exposure equipment malfunctioning could produce erroneous masks, several consecutive mask failures in the worst case. This type of error might unexpectedly increase mask turnaround time. Due to high cost of mask fabrication and its annual growth, it is critical detecting those errors as early as possible. Since mask SEM images at after-development inspection (ADI) phase have more visible noise, edges might be hard to detect clearly using classical edge detection algorithms. In this context, we present a novel pattern error detecting algorithm to capture pattern errors in mask monitoring patterns by inspecting mask SEM images at ADI phase. The originality of this paper lies in its use of simple but powerful techniques in a series used for automated error detection. More specifically, we inspect two specific types of errors in SEM images of monitoring patterns: bridging errors in a chessboard pattern, and CD uniformity errors in a line-and-space pattern. For a chessboard pattern, we utilize both horizontal and vertical projections of image intensity histogram to find areas for inspection automatically. From one dimensional projection of the image, we identify spatial coordinates of our interests, and define a small rectangular region, called D-region. For each D-region, we determine whether a pattern bridge is likely to occur, based on the ratio of brighter pixels in it. For a line-and-space pattern, we compute base lines for CD measurement, and detect CD uniformity errors or line shift errors by applying similar one dimensional histogram analysis and CD-computation algorithm to the image. Our experimental results using real pattern images and programmed defect images support that this technique is effective and robust in detecting errors without layout data or another SEM image for comparison.

Global pattern density control by resizing fill patterns for CD skew compensation

The global pattern density of a mask is a major factor of etch process-induced CD skew. Logic products have different global pattern densities according to the various area portions of SRAM and logic cells. For example, the pattern densities of 66 devices of 130nm node vary from 34% to 47.7% for active layer and from 14.7% to 26.7% for gate poly layer. In order to compensate the global pattern density effect on CD skew, the process condition change is easy to practice for process engineers. But the process condition change for each device increases process variation and reduces process margin. A direct approach to compensate the global density effect on CD skew is necessary. In this paper, we propose a method to make the global pattern density of a mask uniform at the data preparation stage. Our approach is to resize fill patterns to control the global pattern density. We confirmed that the proposed method is effective to control the global pattern densities of masks to a target density within +/- 1%.