Dae-Youp Lee

Effect of cross-link density and hydrophilicity of PU on blood compatibility of hydrophobic PS/hydrophilic PU IPNs

To investigate the effect of the hydrophilic and hydrophobic microdomain structure on blood compatibility, a series of interpenetrating polymer networks (IPNs) composed of hydrophilic polyurethane (PU) and hydrophobic polystyrene (PS) was prepared. One series was prepared with varying cross-link densities of each network, the other with varying hydrophilicity of the PU component. All PU/PS IPNs exhibited microphase-separated structures that had dispersed PS domains in the continuous PU matrix. The domain size decreased with decreasing the hydrophilicity of the PU component and increasing the cross-link density of each network. As the cross-link density and hydrophobicity of the PU component was increased, an inward shift of Tgs was observed, which was due to the decrease in phase separation between the hydrophobic PS component and hydrophilic PU component. In the in vitro platelet adhesion test, as the microdomain size of PU/PS IPN surface decreased, the number of adhered platelets on the PU/PS IPN surface was reduced and deformation of the adhered platelets decreased. It could be concluded that blood compatibility of PU/PS IPN was mainly affected by the degree of mixing between PU and PS component, which was reflected by the domain size of PS rich phase.

Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination

The k1 factor of the 65nm node device approaches to around 0.3 or even below because the device shrinking is much faster than the development speed of the high NA ArF scanner. Since the conventional model-based OPC (MBOPC) is only focused on patterning of the layout on the wafer as exactly same as the original design, it can hardly guarantee enough process margin in the low-k1 lithography regime. In this paper, illumination shape and retargeting rule of the multi-step OPC are optimized to improve the process margin of the 65nm node memory device. Sigma width and open angle of the dipole illumination is optimized to resolve the minimum pitch and to maintain the critical dimension (CD) uniformity. Even though the illumination is optimized and litho-friendly layout (LFL) [1] is applied, there is the process weak point caused by the device architecture. Applying the full-chip level verification, it is found that most of process weak points exist in isolated and semi-dense patterns of the core and peripheral region. The full-chip level verification uses the vector thin film model for the accurate resist image simulation of the high NA scanner. As the mask error enhancement factor (MEEF) is getting larger in the 65nm node device, the mask mean to target (MTT) rises as the dominant factor of the process margin. The NILS according to mask MTT variation is adopted as criterion for the process weak point extraction. Since the NILS of process weak point can be improved by the increasing pattern with, retargeting rules such as selective bias and pattern shift are applied. Under the dipole illumination, the NILS distributions of parallel and perpendicular patterns are different and the different retargeting rules are applied to them. Applying proposed illumination and multi-step OPC optimization to the 65nm node memory device, we have validated that our methodology can insure enough process margin for the volume production.