Suk-joo Lee

Fast and accurate 3D mask model for full-chip OPC and verification

A new framework has been developed to model 3D thick mask effects for full-chip OPC and verifications. In addition to electromagnetic (EM) scattering effects, the new model also takes into account the non-Hopkins oblique incidence effects commonly found in real lithography systems but missing in prior arts. Evaluations against rigorous simulations and experimental data showed the new model provides improved accuracy, compared to both the thin-mask model and the thick-mask model based on Hopkins treatment of oblique incidence.

Double-Patterning Technique Using Plasma Treatment of Photoresist

The double-patterning process was investigated for line-and-space (L/S) patterns of 65 nm half pitch [k1=0.286, 0.85-numerical aperture (NA) ArF dry system] by plasma treatment of photoresist (PR). The sequence of this patterning is exposure–plasma treatment–exposure–etching. Si thin-film passivation and HBr plasma treatment (HPT) were applied, and Si thin-film passivation is preferred to HPT in terms of intermixing prevention and etch selectivity. For planarization of the topographic surface, a thick bottom PR was coated on the pattern after the first exposure. Si thin-film passivation and the thick bottom PR enabled the second exposure to be separated from the first exposure. After the etching process was completed down to the nitride hardmask material, the L/S patterns of 65 nm half pitch were achieved at the full-chip level by virtue of the Si thin-film passivation and thick bottom PR. In the meantime, considering the layout characteristic and process flexibility, layout decomposition and the optical proximity correction (OPC) process were performed. Even though the 65 nm half pitch is defined to be such that k1=0.286, it is believed that this double patterning scheme we suggested can be applied at the minimum pitch over the theoretical limit below 0.25. Consequently, it is expected that the double-patterning technique (DPT) process will have an important role in the extremely low k1 lithography beyond the 32 nm node.

Uniformity measurement of electron emission from carbon nanotubes using electron-beam resist

The field-emission sites’ distribution was measured to monitor the emission uniformity from randomly oriented carbon-nanotube (CNT) emitters using electron-beam resists (ER). The dot-patterned CNT emitters were fabricated by screen-printing a photoimageable CNT paste on an indium doped tin oxide (ITO) coated glass plate. An ER-coated Si substrate used as an anode provides the detection of the location and amount of the electron emission from the partial number of active emission sites among many existing CNTs. The measurements were carried out with the variation of electrical fields through continuous- or pulsed-voltage applications on a diode-type configuration. Developed ER images after a similar dosage of field-emission current flow indicate that emission uniformity is improved as the electrical field is increased. This method suggests that the emission uniformity could be estimated for various conditions of emitter preparation, such as CNT type, paste composition, and dispersion process, as well as th...

Three-dimensional proximity effect correction for large-scale uniform patterns

One of the major limiting factors in electron beam (e-beam) lithography is the geometric distortion of written features due to electron scattering, which is known as the proximity effect. A conventional approach to the proximity effect correction (PEC) is, through 2D simulation, to determine the dose distribution and/or shape modification for each feature in a circuit pattern such that the written pattern is as close to the target pattern as possible. Earlier, it was shown that the 3D PEC, which considers the variation of exposure along the resist-depth dimension, would be necessary for the feature size well below 100 nm. Also, a feature-by-feature correction procedure is too time-consuming to be practical, especially for the 3D PEC of large-scale patterns. In this paper, a new method for the 3D PEC is proposed, which adopts 3D resist profile (instead of 2D exposure distribution) in optimization, but avoids the intensive computation by employing a critical-location-based correction procedure. The proposed...

Enhancement of spatial resolution in generating point spread functions by Monte Carlo simulation in electron-beam lithography

The point spread function (PSF) plays an important role in electron beam lithography, e.g., for the estimation of the resist profile, proximity effect correction, etc. The conventional approach often derives PSFs directly from the Monte Carlo simulation, which might have a limitation in the spatial resolution under a certain size of memory available on a computer. A novel method is proposed to enhance the spatial resolution of PSFs generated from the Monte Carlo simulation without increasing the memory size or changing the simulation software. It exploits the fact that the PSF is radially symmetric and utilizes the concept of integrating the PSF. The integrated PSF is generated by the Monte Carlo simulation, and then the PSF is mathematically derived from its integration. Simulation results show that the proposed method has good potential for providing a practical way to enhance the spatial resolution of the PSF.

Study of process contributions to total overlay error budget for sub-60-nm memory devices

According to the 2006 International Technology Roadmap for Semiconductors, the overlay budget of 60nm memory devices is 11nm. To meet such a tight requirement, the total overlay error budget should be controlled carefully. There are many ways to analyze overlay budget; here, however, a simple but accurate methodology is introduced. In this study, total overlay error budget consists of four major contribution categories: scanner, process, metrology, and mask contributions. Scanner contributions are evaluated by measuring machine-to-machine overlay errors in the conventional way. Process contributions are estimated by inverse reactive-ion etch (RIE) lag and chemical mechanical polishing (CMP) erosion. Metrology contributions are evaluated by overlay metrology tools. Finally, mask contributions represent mask-to-mask misregistration. By applying this methodology to 60nm memory devices, it turns out that process contributions are more than 30% of the total overlay error budget for a contact layer. In this art...

Macro analysis of line edge and line width roughness

Line edge and line width roughness (LER/LWR) is commonly estimated by standard deviation sigma. Since the standard deviation is a function of sample line length L, the behavior of sigma(L) curve is characterized by the correlation length and roughness exponent. In this paper, an efficient and practical macro LER/LWR analysis is implemented by characterizing an arbitrary array of similar features within a single CD-SEM image. A large amount of statistical data is saved from a single scan image. As a result, it reports full LER/LWR information including correlation length, roughness exponent, sigma at infinite line length, and power spectrum. Off-line, in-house software is developed for automated investigation, and it is successfully evaluated against various patterns. Starting with the detailed description of the algorithm, experimental results are discussed.

Impact of registration error of reticle on total overlay error budget

As the overlay specification decreases drastically, it is necessary to consider how the total overlay is influenced by each contributing factor. In particular, it is expected that the contribution on overlay error budget can be quantitatively analyzed in terms of the correlation among registration errors of the reticle. The reticle contribution of about 25% is assessed by the breakdown of the sources of overlay metrology uncertainty through the double exposure technique (DET) process. A positive correlation of around 0.7 mitigates the reticle contribution by 180%, compared to the uncorrelated case. In both DET and double patterning technique (DPT) processes, it is needed to positively correlate the registration errors among many reticles in order to decrease the reticle contribution. To maintain the gain of 180% due to positive correlation, the correlation coefficient requisite has to be increased it is difficult to achieve highly positive correlation among more than three reticles. From an integration po...

Model based OPC for implant layer patterning considering wafer topography proximity (W3D) effects

Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage of non-uniform reflective substrates without bottom anti-reflection coating (BARC). Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without BARC, e.g., implant layer, as technology node shrinks. For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full chip OPC on implant layers.

Measurement technique of nontelecentricity of pupil-fill and its application to 60 nm NAND flash memory patterns

Various pupil-fill measurement techniques are evaluated to monitor non-telecentricity of an illuminator as followings: transmission image sensor (TIS) of ASML, source metrology instrument (SMI) of Litel, Fresnel zone plate (FZP) of Philips, and non-telecentricity measurement technique using traditional overlay marks, which is based on an idea that pattern shift is proportional to the amount of defocus. Based on aerial image simulation with measured non-telecentricity, its effect on sub-70 nm device patterning is discussed. Experimental data shows that some of pupil-fills appear more than 70 milli-radian of source displacement error and it may cause serious pattern shift and/or asymmetry. Detailed descriptions of measurement techniques and experimental results are presented.