Daechul Jeong

A Wideband CMOS Noise-Canceling Low-Noise Amplifier With High Linearity

This letter presents a wideband noise-canceling LNA focusing on canceling IMD2 and IMD3. By using a complementary CMOS parallel push-pull structure, the IMD2 is cancelled. The modified noise-canceling circuit properly suppresses the IMD3. Although the optimum canceling points for the noise and distortions are different, the noise figure is not degraded by the choice. The LNA implemented in a 65 nm CMOS process delivers an IIP2 of 25 dBm, an IIP3 of 5.5 dBm with a power gain of 13 dB and an noise figure of 2.1-3.5 dB in a frequency range from 0.1 to 1.6 GHz. The power consumption is 20.8 mW at 1.2 V and the chip area is only 0.014 mm2.

Highly Linear mm-Wave CMOS Power Amplifier

A Ka-band highly linear power amplifier (PA) is implemented in 28-nm bulk CMOS technology. Using a deep class-AB PA topology with appropriate harmonic control circuit, highly linear and efficient PAs are designed at millimeter-wave band. This PA architecture provides a linear PA operation close to the saturated power. Also elaborated harmonic tuning and neutralization techniques are used to further improve the transistor gain and stability. A two-stack PA is designed for higher gain and output power than a common source (CS) PA. Additionally, average power tracking (APT) is applied to further reduce the power consumption at a low power operation and, hence, extend battery life. Both the PAs are tested with two different signals at 28.5 GHz; they are fully loaded long-term evolution (LTE) signal with 16-quadrature amplitude modulation (QAM), a 7.5-dB peakto-average power ratio (PAPR), and a 20-MHz bandwidth (BW), and a wireless LAN (WLAN) signal with 64-QAM, a 10.8-dB PAPR, and an 80-MHz BW. The CS/two-stack PAs achieve power-added efficiency (PAE) of 27%/25%, error vector magnitude (EVM) of 5.17%/3.19%, and adjacent channel leakage ratio (ACLRE-UTRA) of -33/-33 dBc, respectively, with an average output power of 11/14.6 dBm for the LTE signal. For the WLAN signal, the CS/2-stack PAs achieve the PAE of 16.5%/17.3%, and an EVM of 4.27%/4.21%, respectively, at an average output power of 6.8/11 dBm.

Highly linear CMOS power amplifier for mm-wave applications

Fully-integrated highly linear Ka-band differential power amplifiers (PA) are designed in 28-nm CMOS process. A Class-AB topology is used to increase the efficiency and linearity. For proper operation of the class-AB amplifier, harmonic control circuits are introduced to minimize the 2nd harmonics at the drain and source of the transistor. By adopting this structure, the common source / 2-stack PAs achieve PAE of 27% / 25%, and EVM of 5.17% / 4.2% and ACLRE-UTRA of -33 dBc / -33 dBc, respectively, at an average output power of 9.5 dBm / 14.2 dBm at 28.5 GHz for a 20-MHz bandwidth, 64QAM, and 7.5-dB PAPR LTE signal.

A Handy Dandy Doherty PA: A Linear Doherty Power Amplifier for Mobile Handset Application

As wireless communications progress from second to fourth-generation (4G) systems, the information content drastically increases, requiring high-data-rate transmissions. For efficient use of precious spectrum resources, the modulated signals have wider bandwidths (BWs) and higher peak-toaverage power ratios (PAPRs) than previous generations of systems. Therefore, the power amplifier (PA) operates at a less efficient backoff-power region to achieve the required linearity.

Optimized Ultralow-Power Amplifier for OOK Transmitter With Shaped Voltage Drive

For a highly efficient ON-OFF keying (OOK) transmitter, a microwatt-level ultralow-power (ULP) driver and power amplifier (PA) are designed. For efficient amplification with very high optimum impedance in the ULP application, a class-C topology is implemented and loadpull simulations are carried out to show that the proposed PA can achieve good efficiency at high optimum load impedance without any harmonic tuning. In addition, a voltage-shaping driver is optimized together with the PA for an efficient drive. The proposed driver shapes the PA input voltage into a waveform having a small conduction angle. The shaped input voltage drives the PA to a saturated operation for good efficiency even if the supply voltage is low in the drive stage. The developed driver and PA are implemented in a CMOS 65-nm process and support a 1-Mb/s OOK modulated signal. The implemented PA achieves a drain efficiency of 50.8% at the -6.8-dBm output power and 49.8% at the -10-dBm output power when transmitting continuous 1 signal.

Linear CMOS power amplifier at Ka-band with ultra-wide video bandwidth

A highly linear power amplifier (PA) with ultra-wide video bandwidth is designed at a Ka-band for 5G application. To get a high linearity with high efficiency, a deep class-AB topology with 2nd harmonic control circuits is employed, reducing the 3rd order nonlinearity. Further, an efficient low-drop out (LDO) regulator is proposed to suppress the memory effect generated by the envelope and fundamental nonlinear mixing. The PA, composed of 3 cascaded common-source (CS) stages, achieves peak PAE of 21.8% at output power of 14 dBm with 22 dB gain. The 3rd order inter-modulation distortion (IMD3) at an output power of 5 dBm is under −30 dBc for a video bandwidth of 1 GHz. The PA and LDO are fabricated in a 65 nm CMOS process and occupy 0.53 mm2.

Linear PA at mm-Wave band for 5G application

A highly linear power amplifier (PA) at Ka-band is implemented in 28-nm bulk CMOS process. Operating at a deep class-AB mode with appropriate 2nd harmonic control circuit, a highly linear and efficient PA is designed at mmwave band. This PA architecture provides a linear PA operation closer to the saturated power, providing high efficiency. Also elaborated harmonic tuning and neutralization techniques are used to further improve the gain and stability. A 2-stack PA is designed for higher gain and output power than a common source PA. Additionally, the memory effect of the PA is suppressed to increase the video bandwidth in the GHz range. This amplifier is quite suitable for 5G application.

Ultra-Low Power Direct-Conversion 16 QAM Transmitter Based on Doherty Power Amplifier

This letter presents a fully-integrated umW,ltra-low power (ULP) direct-conversion transmitter. For an ULP modulation, a voltage-driven passive-mixer is optimized with a super source follower (SSF) having a low-output impedance. Also, a linear Doherty PA is proposed for a good back-off efficiency. For transmitting a 16-QAM signal with PAPR of 7.5 dB, the efficiency of the Doherty PA is 14% with the ACLR of -30.1 dBc and the EVM of 5.8% at the average output power of -7.66 dBm. The baseband buffer and the mixer including the non-overlapping 4-phase clock generator consumes 0.59 and 0.51 mW, respectively, and the measured power consumption of the transmitter chain is 2.59 mW. The transmitter is implemented using 28 nm CMOS process and occupies an active area of 0.525 mm2.