Kyunghoon Moon

Linearization of CMOS Cascode Power Amplifiers Through Adaptive Bias Control

Highly linear and efficient CMOS cascode power amplifiers (PAs) are developed for handset applications. The linearity of the PAs is improved using adaptive bias circuits at the gates of the common-source (CS) and the common-gate (CG) stages. The memory effects that are generated by the bias circuits are reduced using second harmonic control circuits at the source of the CS and the gate of the CG stages. The proposed PA, including the integrated bias circuits, is fabricated using a 0.18-μm RF CMOS technology. The adaptive gate bias circuits improve the linearity and efficiency significantly. The measurement results show that the sideband asymmetry is less than 1.5 dB and the peak average power is improved by 1.2 dB within the linearity specification for a 16-QAM 7.5 dB PAPR LTE signal. The bias circuits improve the linearity of the PA within the specification without using digital pre-distortions. The CMOS PA delivers a power-added efficiency (PAE) of 41.0%, an error vector magnitude (EVM) of 4.6%, and an average output power of 27.8 dBm under an ACLRE-UTRA of -31.0 dBc for a 10-MHz bandwidth signal at 1.85-GHz carrier frequency.

Control of IMD Asymmetry of CMOS Power Amplifier for Broadband Operation Using Wideband Signal

A fully integrated linear CMOS power amplifier (PA) for the broadband operation is developed for handset applications. This amplifier can handle a wideband signal. To achieve broadband/wideband operation, an analysis of the intermodulation distortion for the asymmetric source in a differential cascode structure is presented. Based on the analysis, the linearization technique using a second harmonic circuit at the gate of the common gate is proposed to reduce the asymmetry. The proposed PA with an on-chip transmission-line transformer, which has a broadband matching characteristic, is fabricated using a 0.18-μm RF CMOS technology. The measurement results show that the sideband asymmetry is less than 0.6 dB for a signal with up to 50-MHz bandwidth, and the peak average power is improved by 1.2 dB within the linearity spec of a 16-QAM 7.5-dB peak-to-average power ratio long-term evolution signal. The PA delivers a power-added efficiency of 36.5%-31.2% and an average output power of 27.5-27.1 dBm under an ACLRE-UTRA of -30.5 dBc for a 50-MHz bandwidth signal across 1.4-2.0-GHz carrier frequency.

9.5 efficient digital quadrature transmitter based on IQ cell sharing

As new complex communication standards employ various modulation methods in various frequency bands, interest in the software-defined radio (SDR) transceiver to support the standards is increasing. For the flexible transceiver, a digital-intensive transmitter has many advantages and has been pursued intensively. The efficiency of the transmitter chain is strongly dependent on the PA, and switching PAs, such as Class-D and F PAs, are used due to their high efficiency. A polar transmitter is suited for the switching operation and receives a large attention. However, a CORDIC is needed for l/Q-to-Polar conversion, and it is very complex. Moreover, the polar signal has a large bandwidth compared to the l/Q signal bandwidth. On the contrary, the quadrature transmitter that does not require the CORDIC, is simple and low computing cost with low power consumption. Due to the favorable characteristics, the quadrature transmitters have been studied. [1] employs an RFDAC based on a Gilbert mixer. It operates in a current mode and the output impedance varies with the number of on-cells. Due to the impedance variation, it is difficult to have a high linearity. In [2], the input digital code is processed by delta-sigma modulation for smaller digital bits and enhanced resolution. However the modulator generates quantization noise. In [3-6], a voltage-mode transmitter is employed with a power combiner based on a switched capacitor. The output impedance is constant, determined by the total capacitance regardless of the on/off cell condition. Moreover, this architecture delivers much higher output power and efficiency than previously reported works. [4] used delta-sigma modulation with cascade PWM to improve linearity. In [5], a quadrature architecture was employed to eliminate the problems of the polar architecture. Due to the 90° phase difference of conventional digital l/Q LOs, the output power of the conventional quadrature transmitter has lower than that of polar, maximum 3dB lower when the magnitude of I and Q are equal.

Linear Doherty Power Amplifier With an Enhanced Back-Off Efficiency Mode for Handset Applications

This paper presents a linear Doherty power amplifier (PA) with enhanced back-off efficiency mode for handset applications. For linear Doherty operation, we analyze the gain modulation as well as the cancellation of the third-order intermodulation distortion in order to improve the linearity. A compact design method is also discussed to implement on a single chip for a handset. The proposed Doherty PA delivers good performance with regard to the third-generation (3G)/fourth-generation (4G) modulation signals. A switched-load power-mode PA is adopted in the proposed Doherty PA to enhance the efficiency in the low-power region with over 10-dB back-off. For demonstration purposes, the PA is implemented using an InGaP/GaAs heterojunction bipolar transistor and AlGaAs/InGaAs pseudomorphic high electron-mobility transistor process. The PA is tested at 1.85 GHz using both a long-term evolution signal with 16-quadrature amplitude modulation, 7.5-dB peak-to-average power ratio, and 10-MHz bandwidth (BW) and a wideband code division multiple access signal with 3.3-dB PAPR and 3.84-MHz BW. The proposed linear Doherty PA with an enhanced back-off efficiency mode delivers good performance in both the high- and low-power modes, implying that the dual-power-mode Doherty PA configuration can be a promising candidate for extending the battery life of handheld devices in 3G and 4G wireless communication systems.

Analysis of Envelope-Tracking Power Amplifier Using Mathematical Modeling

This paper describes analysis of an envelope-tracking power amplifier (ET PA) to show its operational behavior. The RF PA is modeled by sweeping the input power and supply voltage. The RF PA model is composed of three 2-D lookup tables including the amplitude-to-amplitude modulation, amplitude-to-phase modulation, and amplitude-to-efficiency modulation. The hybrid switching supply modulator is also modeled using an ideal op-amp, ideal switches, and other assisting blocks. Based on the mathematical models of the RF PA and supply modulator, the ET PA can be analyzed with a fast calculation speed and a good accuracy to find the optimum ET operation point. A power control strategy is presented for the optimal ET operation over a broad output power range. The effect of the delay mismatch on the characteristics of the ET PA is also described to assist the time alignment algorithm. For a 10-MHz long-term evolution signal with a 7.44-dB PAPR, the implemented ET PA at 1.71 GHz delivers a PAE of 44.3%, a gain of 29 dB, an evolved universal terrestrial radio access adjacent channel leakage ratio of -35.1 dBc, and an error vector magnitude of 2.91% at an average output power of 28 dBm.

CMOS Saturated Power Amplifier With Dynamic Auxiliary Circuits for Optimized Envelope Tracking

A CMOS saturated power amplifier (PA) is developed for optimally implementing the envelope-tracking (ET) transmitter. The CMOS saturated PA is used to maximize the efficiency of the ET PA. The dynamic feedback control and the biasing techniques at the gates of the common-gate stage and the common-source of the cascode structure are proposed to improve the dynamic range, linearity and efficiency. The fully-integrated CMOS PA with a supply modulator is fabricated using a 0.18- μm RF CMOS technology. For a long-term evolution signal at 1.85 GHz with a 10-MHz bandwidth and a 16-quadrature amplitude modulation 7.5 dB peak-to-average power ratio, the ET-based CMOS PA module delivers a power-added efficiency of 37.6%, an error vector magnitude of 2.4%, and an an evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE-UTRA) of -36.8 dBc at an average output power of 26.5 dBm. The proposed auxiliary circuits enable the ET-based CMOS PA to provide the significantly improved performance.

Enhanced linearity of CMOS power amplifier using adaptive common gate bias control

This paper presents a fully-integrated linear CMOS power amplifier (PA) with an adaptive gate bias circuit in Common-Gate (CG) amplifiers. The bias circuit is proposed to achieve a high linearity with deep class-AB biasing of Common-Source (CS) stage. The proposed single stage PA including the bias circuit is fabricated using 0.18-μm RF CMOS technology. The adaptive gate bias circuit improves the evolved universal terrestrial radio access adjacent channel leakage ratio (ACLRE-UTRA) about 7 dB at a mid power region and 2.5 dB at a high power over a constant bias for the same LTE signal.

Highly Linear mm-Wave CMOS Power Amplifier

A Ka-band highly linear power amplifier (PA) is implemented in 28-nm bulk CMOS technology. Using a deep class-AB PA topology with appropriate harmonic control circuit, highly linear and efficient PAs are designed at millimeter-wave band. This PA architecture provides a linear PA operation close to the saturated power. Also elaborated harmonic tuning and neutralization techniques are used to further improve the transistor gain and stability. A two-stack PA is designed for higher gain and output power than a common source (CS) PA. Additionally, average power tracking (APT) is applied to further reduce the power consumption at a low power operation and, hence, extend battery life. Both the PAs are tested with two different signals at 28.5 GHz; they are fully loaded long-term evolution (LTE) signal with 16-quadrature amplitude modulation (QAM), a 7.5-dB peakto-average power ratio (PAPR), and a 20-MHz bandwidth (BW), and a wireless LAN (WLAN) signal with 64-QAM, a 10.8-dB PAPR, and an 80-MHz BW. The CS/two-stack PAs achieve power-added efficiency (PAE) of 27%/25%, error vector magnitude (EVM) of 5.17%/3.19%, and adjacent channel leakage ratio (ACLRE-UTRA) of -33/-33 dBc, respectively, with an average output power of 11/14.6 dBm for the LTE signal. For the WLAN signal, the CS/2-stack PAs achieve the PAE of 16.5%/17.3%, and an EVM of 4.27%/4.21%, respectively, at an average output power of 6.8/11 dBm.

Investigation of Intermodulation Distortion of Envelope Tracking Power Amplifier for Linearity Improvement

An intermodulation distortion of an envelope tracking (ET) power amplifier (PA) is investigated in this paper. For this purpose, the distortion characteristics are simulated based on the inter-connection model between the PA and supply modulator. For the sweet spot tracking ET operation, the fifth-order distortion is the most important one, which is generated by AM-PM nonlinearity. To reduce the distortion, the phase compensation network (PCN) is proposed. The efficiency of the PA is also improved by a properly designed bias circuit. For demonstration purposes, the PA and supply modulator are implemented using an InGaP/GaAs heterojunction bipolar transistor and a 0.18- μm CMOS process, respectively. The ET PA is tested at 1.85 GHz using a long-term-evolution signal with 10-MHz bandwidth, a 7.5-dB peak-to-average power ratio, and 16 quadrature amplitude modulation. The ET PA with the proposed PCN and the bias circuit delivers a power-added efficiency of 44.3%, a gain of 23.4 dB, an evolved universal terrestrial radio access adjacent channel leakage ratio of -38.4 dBc, and an error vector magnitude of 1.8% at an average output power of 27 dBm. The multiband characteristics of the proposed ET PA are measured across 1.7-2.0 GHz. These results are achieved without any digitally supported techniques, indicating that the design approach is a promising technique for handset ET PA applications.

Highly Efficient RF Transmitter Over Broad Average Power Range Using Multilevel Envelope-Tracking Power Amplifier

We present a highly efficient RF transmitter over broad average power range using a multilevel envelope-tracking power amplifier (ML-ET PA). The ML-ET PA delivers enhanced efficiency at a back-off power region for handset applications. The supply modulator consists of a linear regulator and a switching converter. The DC supply of the linear regulator is adjusted according to the average power of the envelope signal, and the power-supply-independent class-AB output stage is employed to avoid the crossover distortion generated by the different DC supply voltages. The switch current level is not optimally adjusted by itself following the power back-off level, because the DC supply voltages of the linear regulator and switching converter are different. For the optimum operation over the entire power region, the switch current level is adjusted by detecting the input envelope voltage level. For a 20-MHz long term evolution signal with a 7.5 dB peak-to-average power ratio, the proposed supply modulator delivers a peak voltage of 4.5 V to a 6.5 Ω load with a measured efficiency of 75.9%. The proposed ET PA delivers a power-added efficiency (PAE) of 40%, gain of 28.8 dB, evolved universal terrestrial radio access adjacent channel leakage ratio of -35.3 dBc, and error vector magnitude of 3.23% at an average output power of 27 dBm and an operating frequency of 1.71-GHz. At a 10 dB back-off point, the PAE is improved from 14.5% to 18.7% compared to the conventional ET PA.