Daeyun Shim

A dual-loop delay-locked loop using multiple voltage-controlled delay lines

This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty cycle corrector immune to prevalent process mismatches. A test chip has been fabricated using a 0.25-/spl mu/m CMOS process. At 400 MHz, the peak-to-peak jitter with a quiet 2.5-V supply is 54 ps, and the supply-noise sensitivity is 0.32 ps/mV.

An analog synchronous mirror delay for high-speed DRAM application

An analog synchronous mirror delay (ASMD) is proposed, which provides fast locking characteristics in recovery from power-down mode in a DRAM application. As an open-loop fast locking system, ASMD measures and compensates the skew between external and internal clocks in analog operation mode within two cycles of an input clock using a charge-pumping scheme. This ASMD has no static phase error problem, which is related to the path selection operation of previously implemented SMD schemes. To enhance the linearity of delay characteristics and to increase the maximum operating frequency, dual pumping and multiple folding schemes are also proposed. An experimental chip with basic ASMD configuration is fabricated using 0.6-/spl mu/m double-metal CMOS technology to verify the feasibility of the proposed scheme. With functional blocks of the charge pump, comparator, and control pulse generator, it occupies an area of 1.1/spl times/0.7 mm/sup 2/. An experimental ASMD has a working range of 100-300 MHz at 3.3 V with peak-to-peak jitter of 140 ps/spl plusmn/200 mV of sinusoidal supply noise of 1 MHz added, and power dissipation of 30 mW at 250-MHz clock input.

An efficient global motion characterization method for image processing applications

A very hardware and computational efficient method for frame motion characterization is presented. The method replaces the time consuming calculation of two-dimensional m/spl times/n picture elements with that of two one-dimensional vectors. This is made possible by mathematically operating the luminance values of vertical and horizontal lines as the characteristic values of x and y direction respectively; either by taking simply the weighted average values, or taking only those of the above-threshold values. By comparing these characteristic values taken from two frames in a sequence of moving pictures, one can extract the components of frame changes quantitatively into three factors; the factor caused by the motion of objects, or the factors caused by the panning, or zooming of the camera. The efficiency of this algorithm is examined with some practical examples, and application possibilities in an automatic motion tracking system and image stabilizer are discussed.

A low jitter dual loop DLL using multiple VCDLs with a duty cycle corrector

A low jitter dual loop DLL with multiple VCDLs has been developed. This DLL whose locking range is 150-600 MHz, allows unlimited phase shift without noise sensitivity issues. A built-in duty cycle corrector guarantees 50% duty cycle under severe transistor mismatch.

Fast locking clock generator using analog synchronous mirror delay technique with feedback control

With dual pumping ASMD as a core block, the proposed clock generator shows no phase quantization problem and also does not require replica of clock network. Also duty cycle correction is performed using selectable delay line with serial phase blend techniques. To verify the functionality of the proposed scheme, test chip is fabricated using 0.25 /spl mu/m 5 metal CMOS technology with 2.5 V supply. The measurement shows static phase error of <50 ps with frequency range of 250 MHz to 500 MHz having peak-to-peak jitter of 80 ps without external supply noise and that of 120 ps with /spl plusmn/500 mV 1 MHz rectangular noise at 333 MHz.

The design of 16/spl times/16 wave pipelined multiplier using fan-in equalization technique

In this paper, a wave-pipelined 16/spl times/16 multiplier is presented. The critical problem of wave pipelining, the cumulative delay deviation of each stage, is minimized by using fan-in equalization technique. A new logic cell concept, Tree Pass transistor Logic (TPL), is employed as a wave pipeline circuit element, whose speed is comparable to CPL, and whose logic style is similar to that of DPL. Also a new true single phase flip-flop is proposed which enables one to reduce the number of registers to a half of conventional wave pipeline configuration. The wave pipelined 16/spl times/16 multiplier of total 31,400 transistors, is comprised of input-fanin equalizer, 8 modified Booths encoder, 2 level of (4:2) compressor and 28 bit fast adder. At 3 V supply, the estimated throughput rate of 500 MHz is obtained by SPICE simulator using typical parameters of 0.8 /spl mu/m technology and practical considerations.

A load-adaptive, low switching-noise data output buffer

This paper describes a data output buffer which shows a reduced switching noise over wide-range of loading conditions. The proposed output buffer employs load-adaptive circuitry to achieve bounded delay regardless of loading condition. For that purpose, a load monitoring circuit is embedded in the output buffer. The adaptive control of driving current enables the switching noise to be kept at a minimum value. The experimental chip with a 0.61 /spl mu/m CMOS technology shows a reduced switching noise level, 15%/spl sim/35% of conventional buffer while the transition time is bounded within 7 ns for loading capacitance up to 100 pF.