Ook Kim

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-/spl mu/m CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply.

A 3.3 V 0.8 /spl mu/m CMOS single chip IF IC for CDMA/FM cellular phone

A 3.3 v 150 mW IF IC is implemented using 0.8 /spl mu/m CMOS process. This IC integrates both CDMA and FM IF signal processing units and interfaces between IF signals and baseband modem. Rx mixer down-converts 85.38 MHz IF signals into baseband signal, and Tx mixer based on a replica transconductor up-converts baseband signal into a 130.38 MHz IF signal. The chip size is 5.5/spl times/6.3 mm/sup 2/.

A Digital Self Compensation Circuit for High Speed D/a Converters

This paper presents a digital self compensation method for video-rate D/A converters(DACs). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.